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PostPosted: Fri Feb 02, 2024 1:54 pm 
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Hello everyone. A (quick) search came up with nothing, so newbie question here:

In my efforts to increase the speed of my bootloading processes (from here viewtopic.php?f=4&t=7939), I'm thinking of doing unconventional things to the '816.

What if I hold BE low during all read cycles? Will whatever is on the databus still reach the internals of the 65816?

Here is a step by step:

Code:
*** Setup ***
Ground PHI2, BE, and /RES     // initial conditions
Toggle PHI2 high then low, about 20 times, doesn't matter     // just making sure everything is cleared out
Drive external databus     // coming from outside source
Put $EA on databus (reset vector will end up being $EAEA, doesn't matter)     // this will eventually be NOP instructions
Release /RES to pull high     // bring out of reset
Toggle PHI2 high then low, about 20 times     // I think that you cannot know exactly how many cycles it will take until /VP goes low?
Check VDA and VPA, if both low then toggle PHI2 high then low one time     // if in the middle of a NOP instruction, cycle once more

*** Bootload Read ***     // the idea here is to use LDA# and STAal instructions to reach specific RAM addresses
Put $A9 on databus (LDA# instruction)
Toggle PHI2 high then low
Put desired data value on databus
Toggle PHI2 high then low
Put $8F on databus (STAal instruction)
Toggle PHI2 high then low
Put desired low addr on databus
Toggle PHI2 high then low
Put desired high addr on databus
Toggle PHI2 high then low
Put desired bank addr on databus
Toggle PHI2 high then low

*** Bootload Write ***     // at this point R/W would be low
Tristate external databus
Release BE to pull high
Toggle PHI2 high then low     // this is where the '816 writes to RAM
Ground BE
Drive external databus

Loop back to "Bootload Read"


I read the datasheet and they mention Data/Address Buffers, but it's unclear if inhibits incoming signals and not just outgoing signals. Hypothesizing, I'd say the A0-A15 and R/W lines would be cut off entirely, because they are output-only signals. But what about that bi-directional D0-D7 bus?

Thank you for any insight!

Chad

EDIT:

Looking at the Rockwell datasheet (here https://web.archive.org/web/20221112220 ... essors.pdf) there is the timing diagram for BE on page 1-15 (see attached picture), which has A0-A15 and R/W going into tri-state, but the databus is oddly absent. Hm.


Attachments:
BE-Timing.png
BE-Timing.png [ 52.11 KiB | Viewed 1613 times ]
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PostPosted: Sat Feb 03, 2024 3:33 am 
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sburrow wrote:
I'm thinking of doing unconventional things to the '816.
Attaboy, Chad! :twisted:

Sorry I'm rushed ATM, and haven't fully reviewed the details of what you're proposing here. But as for...
Quote:
What if I hold BE low during all read cycles? Will whatever is on the databus still reach the internals of the 65816?
... I'm inclined to say the answer is yes. I mean, if the answer were no, what could possibly be the reason?

I can't imagine the chip designers included any extra logic specifically to accommodate the extraordinary circumstance of inputting data from a bus access that's been prevented from outputting an address! Virtually nobody is worried about this, so they have no incentive. And even if they for some reason did want to do something about it, what remedy could they apply?

From another line of reasoning, the simplest way to implement BE is to merely run that signal to the on-chip logic that enables the output buffers. Doing so will provide the functionality that users require, and I can't imagine why they'd wanna run BE anywhere else. But perhaps my imagination is having an off day today!

-- Jeff

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PostPosted: Sat Feb 03, 2024 7:09 am 
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sburrow wrote:
What if I hold BE low during all read cycles? Will whatever is on the databus still reach the internals of the 65816?

...

Like Jeff, I can’t write a detailed dissertation right now.  What I will say that in the world of 65xx timing, the high-to-low clock transition is the timing base, not low-to-high.  Hence when it comes to counting cycles that must elapse in order for something to happen, you count from the fall of the clock.

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PostPosted: Sat Feb 03, 2024 8:16 am 
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A thought though: what's the internal mechanism to control the lines? If it's an actually enabled driver, fair enough, but I suspect it might be cheaper and simpler if transmission gates were used... in which case, they'd be open circuit both ways. And transmission gates, I believe, use only a single transistor instead of the half-a-dozen for a bidirectional driver.

Kinda like the difference between a 245 and cbt3245 - the latter is faster, but provides no drive; it's just a switch to upstream logic.

Neil (who is most definitely not an expert in chip internals)


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PostPosted: Sat Feb 03, 2024 9:27 am 
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I think for me the most likely answer is that BE disables the output drivers, and that won't affect the inbound data. I'm not quite sure how you plan to make use of this but an initial experiment will probably enlighten both of us!


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PostPosted: Sat Feb 03, 2024 2:06 pm 
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Thank you for the responses!

As per Ed's suggestion, an experiment seems to be needed. I had one 'spare' pin on the CPLD which had a pull-down resistor on it, but it's good enough to test. I connected it to BE on the 65816, and then in verilog code I did this:

Code:
assign be = (~boot) ? (phi2 && rw ? 1'b0 : 1'b1) : 1'b1;


Basically while bootloading, it will make BE go low if PHI2 is high and R/W is high, thus reading. Otherwise BE is high.

And, it worked! It loaded everything off of the PIC without any issue. I don't know if I'd say it's 'proof', but definitely suggests that you all are right, BE only inhibits the output buffers, it does not hinder input.

[ Another note, the CPLD is driving BE at 3.3V, which seems to be ok enough for the 5V '816 right now. Hm! ]

Problem mostly solved. Thank you everyone, good discussion!

Chad


Attachments:
20240203_080010.jpg
20240203_080010.jpg [ 2.32 MiB | Viewed 1537 times ]


Last edited by sburrow on Sat Feb 03, 2024 2:15 pm, edited 1 time in total.
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PostPosted: Sat Feb 03, 2024 2:10 pm 
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great result!


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