6502.org • View topic - Which flag bits are set by the PLP instruction on 6502?

View unanswered posts | View active topics

Board index » 6502.org Users Forum » Newbies

All times are UTC

Which flag bits are set by the PLP instruction on 6502?

Page 1 of 1

[ 4 posts ]

Previous topic | Next topic

Author

Message

randomkiwi

Post subject: Which flag bits are set by the PLP instruction on 6502?

Posted: Tue Dec 26, 2023 1:02 pm

Joined: Thu Oct 26, 2023 5:39 pm
Posts: 5

I was going through the instruction set of 6502 at https://www.masswerk.at/6502/6502_instruction_set.html#PLA . Now below the PLP (Pull Processor Status from Stack) instruction, it is stated that

Quote:

The status register will be pulled with the break flag and bit 5 ignored.

As far PLA instruction is concerned, it is clear that status bit N and Z will be affected by the operation, but I am unable to understand which bits will be affected by the PLP instruction.

Top

gfoot

Post subject: Re: Which flag bits are set by the PLP instruction on 6502?

Posted: Tue Dec 26, 2023 1:26 pm

Joined: Fri Jul 09, 2021 10:12 pm
Posts: 741

The status register only really has 6 bits - C, D, I, N, V, Z - and they are all affected by pulling it from the stack, each being set to the value of one of the bits in the value pulled. The values of bits 4 and 5 in the byte from the stack are discarded.

Top

BigEd

Post subject: Re: Which flag bits are set by the PLP instruction on 6502?

Posted: Tue Dec 26, 2023 1:31 pm

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10985
Location: England

PLP brings in six bits as literals from the byte on the stack: NV—DIZC
The other two bits of the byte have no effect.

(By way of illustration, you wouldn’t normally see both Z and N set, but you could set them both with PLP)

Edit oops crossed in post!

Top

BigDumbDinosaur

Post subject: Re: Which flag bits are set by the PLP instruction on 6502?

Posted: Tue Dec 26, 2023 5:46 pm

Joined: Thu May 28, 2009 9:46 pm
Posts: 8504
Location: Midwestern USA

randomkiwi wrote:

I was going through the instruction set of 6502 at https://www.masswerk.at/6502/6502_instruction_set.html#PLA . Now below the PLP (Pull Processor Status from Stack) instruction, it is stated that

Quote:

The status register will be pulled with the break flag and bit 5 ignored.

As far PLA instruction is concerned, it is clear that status bit N and Z will be affected by the operation, but I am unable to understand which bits will be affected by the PLP instruction.

As the others noted, bits 4 and 5 are not “real” bits in the 6502/65C02—and in the 65C816 when the latter is operated in emulation mode. Bit 4 only exists in the stack copy of the status register (SR) that is pushed during a response to an IRQ or as part of executing a BRK (software interrupt) instruction. If an IRQ is being processed, bit 4 will be clear, otherwise bit 4 will be set. This behavior enables the IRQ/BRK service routine to distinguish between the two interrupt types.

When SR is pulled from the stack with a PLP instruction, bits 4 and 5 will not be affected by whatever is on the stack. The sequence PHP - PLA will result in bits 4 and 5 always being set in the accumulator copy of SR.

For detailed information on the 65xx instruction set, get yourself a copy of “Programming the 65816, Including the 6502, 65C02, and 65802” by Eyes & Lichty. I usually caution people about getting this kind of information from arbitrary websites, as such sites may propagate errors posted on other sites. The Eyes & Lichty manual may be considered authoritative for all permutations of the 6502.

_________________
x86? We ain't got no x86. We don't NEED no stinking x86!

Top

Page 1 of 1

[ 4 posts ]

Board index » 6502.org Users Forum » Newbies

All times are UTC

Who is online

Users browsing this forum: No registered users and 6 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum