6502.org Forum Projects Code Documents Tools Forum
It is currently Sat Nov 23, 2024 12:20 pm

View unanswered posts | View active topics


Board index » 6502.org Users Forum » Newbies

All times are UTC




Post new topic Reply to topic  Page 1 of 1
  [ 7 posts ] 
  Previous topic | Next topic 
Author Message
Yuri
PostPosted: Mon Dec 11, 2023 3:41 am 
Offline
User avatar

Joined: Tue Feb 28, 2023 11:39 pm
Posts: 257
Location: Texas
So I'm about to get some 32Mhz oscillators and try and boost my 6502 from 6.29375MHz up to 8Mhz.
I was reviewing the timing notes of my parts, particularly the ROM which is asking for a 150ns setup time and I got to wondering.

At 6.29375Mhz the whole period is about 159ns (minus some change)
Would I be correct in understanding that each horizontal edge of the clock is about 80ns (give or take rise/fall times)?

Further it would seem from the 6502 data sheets, that @ 8MHz there is about 40ns for the address to be setup, and then about 10ns for it to be valid.
4Mhz suggests these are 75ns and 10ns, still a far cry from the 150ns that the ROM data sheet asks for.

So my basic question is:
Am I effectively overclocking my ROM?

I'm not implementing any clock stretching, though I have noticed when I single step the clock, the address lines seem to hold for two clock cycles while the 6502 does it's internal thing.

IDK if the bus is actually floating during this time and I'm just seeing a latent charge or what, but I'm wondering if this side effect is effectively enough time to let the ROM do its thing.

Thanks


Last edited by Yuri on Mon Dec 11, 2023 3:44 am, edited 1 time in total.

Top
 Profile  
Reply with quote  
Yuri
PostPosted: Mon Dec 11, 2023 3:43 am 
Offline
User avatar

Joined: Tue Feb 28, 2023 11:39 pm
Posts: 257
Location: Texas
Probably would help to provide the datasheet for the ROM I'm using. Here it is.


Attachments:
AT28C64B-15PU.pdf [231.65 KiB]
Downloaded 72 times
Top
 Profile  
Reply with quote  
GARTHWILSON
PostPosted: Mon Dec 11, 2023 3:49 am 
Offline
User avatar

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8545
Location: Southern California
You might find your answers in this post and the ones that follow:
viewtopic.php?p=58784#p58784

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?
Top
 Profile  
Reply with quote  
BigDumbDinosaur
PostPosted: Mon Dec 11, 2023 4:59 am 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8509
Location: Midwestern USA
Yuri wrote:
So I'm about to get some 32Mhz oscillators and try and boost my 6502 from 6.29375MHz up to 8Mhz...

You should clarify if “6502” refers to the NMOS part or the 65C02.

As for whether you are “overclocking” your EEPROM, use the most pessimistic timing specs for the EEPROM and the most optimistic specs for the MPU to calculate how fast you can run with that particular EEPROM without violating its timing.  Be sure to account for propagation delays through your glue logic.  It’s nothing more than basic math and understanding what the data sheet is telling you.  :D

As Garth notes in the post he referenced, the manufacturer guarantees that the device will perform as specified.  Any given device may well perform better than specified, sometimes a lot better—I’ve run into that on occasion.  However, you can’t bank on it.  How far you are willing to push the limits depends on how much stability you are willing to sacrifice.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!
Top
 Profile  
Reply with quote  
Yuri
PostPosted: Mon Dec 11, 2023 5:27 am 
Offline
User avatar

Joined: Tue Feb 28, 2023 11:39 pm
Posts: 257
Location: Texas
BigDumbDinosaur wrote:
Yuri wrote:
So I'm about to get some 32Mhz oscillators and try and boost my 6502 from 6.29375MHz up to 8Mhz...

You should clarify if “6502” refers to the NMOS part or the 65C02.

As for whether you are “overclocking” your EEPROM, use the most pessimistic timing specs for the EEPROM and the most optimistic specs for the MPU to calculate how fast you can run with that particular EEPROM without violating its timing.  Be sure to account for propagation delays through your glue logic.  It’s nothing more than basic math and understanding what the data sheet is telling you.  :D

As Garth notes in the post he referenced, the manufacturer guarantees that the device will perform as specified.  Any given device may well perform better than specified, sometimes a lot better—I’ve run into that on occasion.  However, you can’t bank on it.  How far you are willing to push the limits depends on how much stability you are willing to sacrifice.


I'm using the 65C02.

Right, and I do get that some parts may perform better than others for various reasons, and that the data sheets specify what the manufacturer grantees the part for.

More to the point, I want to make sure I'm actually reading these sheets and mathing this correctly. Thus, did I get lucky and got a particularly spry ROM that is fine with operating at near half the time it says it should, or am I doing my math wrong?

That was the origin of the question.
Top
 Profile  
Reply with quote  
BigDumbDinosaur
PostPosted: Mon Dec 11, 2023 6:51 am 
Offline
User avatar

Joined: Thu May 28, 2009 9:46 pm
Posts: 8509
Location: Midwestern USA
The 150ns rating of that particular EEPROM represents the amount of time that will elapse from when the device’s address, /CS and /OE inputs have stabilized until it drives the data bus.  In a circuit with the 65C02, as long as the EEPROM can produce output at least tDSR nanoseconds before the next fall of the clock, a read operation should be successful.  tDSR is 10ns with the MPU running on 5 volts.  Hence the EEPROM must have stabilized the data bus no less than 10ns before the fall of Ø2 in order for the MPU to be able to read valid data at the fall of the clock.

The point in the clock cycle at which the 65C02 will place an address on the bus after the fall of the clock is defined by the tADS spec.  That number is 30ns, worst case, on 5 volts.  Simplified, the elapsed time from tADS to tDSR is the “window” during which the EEPROM’s /CS and /OE inputs must be asserted, and the device itself must respond and drive the data bus.  If the EEPROM can’t drive the data bus by the end of that window, the MPU will likely see garbage.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!
Top
 Profile  
Reply with quote  
BigEd
PostPosted: Mon Dec 11, 2023 8:28 am 
Offline
User avatar

Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10986
Location: England
Yuri wrote:
...I want to make sure I'm actually reading these sheets and mathing this correctly. Thus, did I get lucky and got a particularly spry ROM that is fine with operating at near half the time it says it should, or am I doing my math wrong?

Indeed, with a 150ns ROM, you're out of spec to run at 8MHz. But as noted, this will often work, in part because of how specifications are drawn up and how chips are made and tested, and in part because you're not running at extreme temperature and voltage.
Top
 Profile  
Reply with quote  
Display posts from previous:  Sort by  
Post new topic Reply to topic  Page 1 of 1
  [ 7 posts ] 

Board index » 6502.org Users Forum » Newbies

All times are UTC


Who is online

Users browsing this forum: No registered users and 22 guests

You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
cron
6502.org is an ongoing project by Mike Naberezny and contributors.