Hey everyone.

Newbie question here: Does it matter if you change the W65C22S VIA's RS and CS lines between PHI2-rising edge and PHI2-falling edge?

Breakdown:

- PHI2 is low, RS and CS lines are set appropriately.
- PHI2 rises.
- PHI2 is high, RS and CS lines change.
- PHI2 falls.

Did it still work correctly?

What if the lines change temporarily, but go back to their original configuration by PHI2 falling edge?

What if only the RS lines change, not the CS lines?

Attached is the timing diagram from the datasheet. It seems to imply that they need to NOT change, but I'm just wondering if that assumption is correct.

EDIT: Another question, does it matter what is on the data bus when PHI2 rises? The diagram seems to imply it does not matter, but just checking.

Thank you everyone!

Chad

At least to the second (edited) question, I'm thinking that the VIA is NOT driving the data bus until PHI2-high. Attached is a screenshot from the Synertek datasheet found here:

http://archive.6502.org/datasheets/syne ... 78_jan.pdf

I believe the WDC datasheet implies this too with it's "tCDRData Bus Delay" from the Timing diagram.

Still not seeing a direct answer to the first question though. Either way, thank you for reading.

Chad

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What's an additional VIA among friends, anyhow?

I'm with Garth -- don't know if the control signals actually get latched on that edge or not.

But implementing a latch would cost some additional silicon, and I can't see that there'd be any payoff. Why would the designers bother to latch signals which, in virtually all scenarios, will remain stable during the Phi2-high time anyway? It seems like a misguided use of resources, and therefore is awfully unlikely, IMO.

Yes the VIA's requirement that RS, CS and R/W be stable before Phi2 rises could perhaps be interpreted to imply that a latch exists. But offhand I tend to suspect that it instead has to do with avoiding destructive writes to the internal registers (and indeed even destructive reads, as of the IFR, for example).

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Can't quite agree! A latch, in NMOS, is a single transistor(*). And for a signal to have meaning inside the chip in the following cycle, that signal needs to keep its value. So a transparent latch clocked with phi2 is exactly what's needed to capture the value as of the falling edge, to have a value inside the chip which is stable for the next half-cycle. The 6502 does exactly this with the RDY input.

Which is not to say anything definitive about the insides of a via. I've a feeling we do have a mega-thread somewhere around here where polygons were extracted and circuit diagrams captured... yes, of course we do:

MOS 6522 dissection //NMOS



Edit: and indeed, in the case of the 6522, in the giant overview schematic png file, we see that the address lines and the RnW and chip select inputs are captured by a transparent latch clocked by... phi1. So, they need to be valid by the rise of phi2. Internally, those latched signals are stable throughout the second half of the cycle.

Edit: perhaps see also
From the vaults: MOS 6522 problems and corrections
Unknown and short-lived MOS6522 Revision 1 (vs. Rev. 0)
list of chip dissections

(*) But note that in the case of the 6522 inputs, we're told that fully static transparent latches are used.

Alright, thanks for the additional info, Ed. And -- to my surprise -- it seems the answer to Chad's question -- "Did it still work correctly?" -- is yes!

Although it's implicit in your post, it wasn't until I examined Dieter's "cheat sheet" (logically equivalent diagram) posted here that I realized that register writes get postponed. All register reads occur in real time (while the incoming Phi2 signal is high), but register writes get postponed by a half cycle.
Clearly the latching for writes is essential, because the incoming signals (RS etc) will be in transition to the next cycle when the (postoned) write occurs.

But, perhaps because I've had only one coffee so far this morning, I see no reason why those signals won't be stable during reads. IOW, it seems to me that the first level of latching could -- except for Chad's highly atypical needs! -- simply be eliminated, as shown on the right below. This is the seemingly "misguided use of resources" I referred to.

Maybe the designers believed or assumed that the extra level of latching would result in a part that's more forgiving to use -- more glitch resistant. Certainly the extra level of latching does no harm. So, from that POV, any change would be an improvement...

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The only possible circa mid 1980's advantage that comes to my mind -- and I don't know if it would work or not -- would be if it helps interfacing with an original PIC style bus from the early 80's, so the PIC address stage pPhi1/pPhi2 is 6522 Phi1, and data pPhi1/pPhi2 is 6522 Phi2.

But by the late 1980's, after MicroChip was spun off with the PIC as a primary product line, the 40pin PIC's with the weird external mixed address/data bus were on their way out and the modern PIC's with the steadily proliferating variety of internal I/O and the data bus strictly internal to the MCU took their place.

Garth, Ed, Jeff, and Bruce, thank you for the detective work!

Jeff I'll be primarily responding to the last post you made.

A longish while ago I was watching a video by Adrian Black repairing / fixing an X16 prototype board. They were having problems with the VIA in particular, and Adrian figured out that they were using a "qualified" R/W signal with PHI2 instead of the "unqualified" R/W signal straight from the 6502.

The video is cued up to around the 26 minute mark, where he starts talking about it. Around the 29 minute mark is when he says exactly what went wrong.

https://youtu.be/LU5989eVRZs?si=GwBaxGDiUHs756t8&t=1547

I had made mention of this to Garth when I found it, how this sort of thing is 6502 Primer 101 stuff. But moving back to our discussion here.

If the rising PHI2 edge is not used on the VIA, then why does it not work when the R/W line is not correctly set at that time? But perhaps I'm misinterpreting Dieter's logic diagrams.

Knowing this, I figured that perhaps the PHI2 rising edge is where the RS/CS lines were latched, and any changes while PHI2 is high doesn't matter. But Jeff is saying that it's the PHI2 falling edge where things are latched! And maybe I'm misunderstanding again, that the RS/CS lines are latched on the PHI2 rising edge, and the data bus is latched on the PHI2 falling edge?

So, it's still a confusing situation!

Lastly, it's not that I *need* these lines to change mid-stream, but I ran into a logic situation where there *could* have been something changing unless I modified it. That's when I posed this question, more out of curiosity than requirement.

Thank you everyone!

Chad

Yup, that's right. And, although I didn't view the video you linked, I expect that's why the folks ran into trouble. If R/W or either of the Chip-Selects signals is qualified by Phi2 then they won't go true until after the Phi2 rising edge. And the Phi2 rising edge is when the window closes on the first set of latches; they switch from "follow" to "hold" (in the same way a 74_373 will do when its E input goes low). Because of the "hold" condition, the signals won't be "seen" as being true -- hence the trouble. They need to be valid before Phi2 rises (and the VIA datasheet specifies this).

There's a further wrinkle, but it's internal to the VIA, and luckily it doesn't really concern us. But if you're curious, have another look at what's already been posted, bearing in mind that each of the two levels of latching in the excerpt of Dieter's diagram corresponds to a 74_373. I admit it's perhaps confusing, as he's using alternative names for the clock signals as they exist internally within the chip. But the first level of latching (on the left) switches from follow to hold when the incoming Phi2 signal from the CPU rises, and the second level of latching (on the right) switches from follow to hold when the incoming Phi2 signal falls. Hope this helps...

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Ok, I think I understand now. RS, CS, and R/W signals are latched on PHI2 rising edge. Data bus is latched on PHI2 falling edge. The data bus is not driven unless PHI2 is high on a 'read' cycle (reading from 6522 into the 6502). Any activity outside of these standards is ignored.

Interesting! Thank you Jeff, this helps a lot. Neat to understand the inner workings a bit more.

Chad

I was thinking that one possible advantage might be if you want to use a serial shift register to avoid the "double tap" of 65C22 reads and writes if putting it on a Z80 bus.

Except ... when I looked closer, it's not needed.

The "double tap" happens because the Z80 adds an automatic wait state during an /IOREQ ... otherwise there wouldn't be adequate time after the /IOREQ for an I/O device that needs wait states to assert the wait state when the Z80 needs it ... and a "naive" connection of a 6522 to a Z80 bus will do two consecutive writes or two consecutive reads at the same register address during the wait state T cycle and the T3 when the action is supposed to be happening.

You can fix this with a shifter or counter circuit output line that changes from low to high on the second clock transition ... inverting that line for the 6522 active low /CS or using it for the 6522 active high CS, and using /CS itself to drive the CLR so that it always starts counting the first clock cycle after the original /CS drops.

The problem is that if it transitions on Phi2 falling, there can be a race between /IOREQ that /CS will have been derived from and the falling edge of PHI2. And if it transitions on Phi2 rising, it won't be set up at the rising edge of T3. So if there is a master clock that is PHI2*2, the ideal is to generate a clock that is 90 or 270 degrees out of phase and use that for the transition.

And my first thought was, "it's halfway out of phase, it will toggle back the other way halfway through PHI2, so it's a good thing that /CS is already latched by the 6522".

But ... my first thought was wrong. The latching of /CS is entirely unnecessary for this to work, because the shifter or counter won't change transition again until halfway through the following PHI1, so /CS will stay low all the way through the PHI2 phase, including a healthy hold at the end.

Indeed, if you use a counter, the count is %0000 -> %0001 -> %0010 -> %0011, so if the /CS comes from the inverse of QB, it is sure to stay low until /CS itself rises and the counter is cleared.