sburrow wrote:
According to the datasheet, if /WE is held low, it needs a minimum of 45ns to write when /CE falls.
This is how long you should hold them low concurrently to assure a stable write. It doesn't mean that shorter times won't write, or won't have nasty side effects which is also possible.
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What I am doing (essentially) is having /WE rise while /CE falls at (essentially) the same time. On this chip, I am getting a write. The /WE pin is not ever floating, nor the /CE pin. 45ns MINIMUM. I am pretty sure that my design does not have that happening. Could be wrong.
In an analogue world, nothing ever really happens simultaneously. If you initiate a rise of /WE at the "same time" as a /CE fall, then they will both be transitioning together, and may very well both be below a threshold for a period of time, and the rate of transition will depend upon things like how many devices are connected to that net, trace capacitance, etc.
For things which are level-triggered like this, it is best to try to ensure both signals are high for at least a short period.
FWIW I strongly suspect that memory chip manufacturers are not really charecterising their chips very carefully, at least for these legacy parts, and the datasheets mostly look like generic "this is how standard memory works" specifications rather than anything specific to the individual chip.
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Could this/these chip(s) latch or hold the /WE signal for longer than intended? Could it see me bringing /WE low as "you want to write, just give me the /CE signal" and instead of acting like an "active low" it instead acts like "falling edge" to write?
No I don't think it's latching anything deliberately, that's against the standard protocol for these kinds of chips as implemented by a variety of manufacturers. It's more likely that the transitions take a while both in the wires and inside the chip itself and it needs a little breathing room between these transitions to guarantee it doesn't see an overlap.
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This particular 62256 chip I have has been known to be super fast. When using other SRAM chips I haven't needed to qualify /WE with more than PHI2. But with this particular chip I have needed to qualify /WE to the second-half of PHI2. But this current behavior is just strange to me.
Typically you qualify /WE with PHI2 but /CE should transition as soon as the CPU puts an appropriate address on the bus (plus your decoding logic). In cases like my video circuits where CE can't transition until PHI2 starts, I delay /WE until at least halfway through PHI2 so that the address decoding has a chance to settle down first as that too can spuriously activate random components very briefly while the address lines are transitioning.
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Is there any way to test the actual speed of this chip with a TL-866II Plus programmer + 'minipro' perhaps?
I'm not sure, even if there was though I wouldn't advise it except for interest's sake - you should make your design more conservative, and it will then deal better with ranges of temperature, replacement components, wear and tear, and other additions to the circuit. (Not that I always get that right! But this is what I've learned.)