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willie68
PostPosted: Mon Oct 31, 2022 3:36 pm 
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Hi there,

i have a strange problem.
i'm working on my W6502SBC code, implementing Wozmon.
But first I wanted to make sure that the W65C51 (incl. adapter) works properly.
So I created a few small routines that write and read.
The write part now works satisfactorily. The only problem is the reading part.
The status register always returns a $30, i.e. (due to the transmit bug) unfortunately bit 3 ($08) is never set, no matter what I send via USB/serial adapter.
And if I still read the RDR I always get a #$02.
Hardware-wise everything seems OK, I can see with my oszi the signal from pin 12,
What am I doing wrong?
Here is the code:

Code:
do_serinit:
    pha
    ; ACIA setup
    stz ACIA_STATUS
    lda #%00011110         ; 8-bit, 1 Stop bit, Baudrate, 9600 Baud
    sta ACIA_CONTROL
    lda #%00001011         ; no parity, no echo, transmit irq disabled, no receiver irq, DTR High
    sta ACIA_COMMAND
    pla
    rts

main block:
Code:
   lda ACIA_STATUS
   jsr lcd_bhexout  ; just to see the content of the status reg in my LCD
   lda #" "
   jsr lcd_chrout

   ldy #$ff
@SERINL1:
   dey
   beq @SERIN3         ; don't block the reciever
   lda ACIA_STATUS     ; Check to see if the buffer is full
   and #$08                ; mask rx buffer status flag
   BEQ @SERINL1
@SERIN3:
   lda ACIA_RX
   jsr lcd_bhexout ; showing the A as Hex on my LCD
   jsr ser_chrout   ; sending A as chr 

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BigDumbDinosaur
PostPosted: Mon Oct 31, 2022 4:51 pm 
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willie68 wrote:
But first I wanted to make sure that the W65C51 (incl. adapter) works properly...

You sure you have a good 6551? From where did you get it? Also, can you post a schematic of how you have the 6551 interfaced to your system?

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willie68
PostPosted: Mon Oct 31, 2022 5:04 pm 
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After 5 china r65c51, no one works correctly, I bought a W65C51 plcc28 version from mouser.de, build an plcc28/dil adapter. Interface clock generation seems OK, because transmit is working correct. Schematic is here
download/file.php?id=15678&mode=view

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8BIT
PostPosted: Mon Oct 31, 2022 6:17 pm 
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I believe the DCDB input must be low for the receiver to work (check the datasheet) Not sure how your hardware is wired using the ftdi, it does not show the DCDB connection.

Daryl

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BigDumbDinosaur
PostPosted: Mon Oct 31, 2022 9:29 pm 
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willie68 wrote:
After 5 china r65c51, no one works correctly, I bought a W65C51 plcc28 version from mouser.de, build an plcc28/dil adapter. Interface clock generation seems OK, because transmit is working correct. Schematic is here
download/file.php?id=15678&mode=view

You’ve got IRQB on your 65C22 wired directly to the MPU’s IRQB. The part number you list for the 65C22 is the ‘S’ version of the device, which has a totem-pole IRQ output. That will not work as expected, since the 65C22 will continuously drive IRQB high unless it is actually interrupting. If a device with an open-collector IRQ output interrupts—the 6551 falls into that category—it will attempt to sink the 65C22’s IRQ output. You should be able to surmise what will likely happen.

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willie68
PostPosted: Tue Nov 01, 2022 8:10 am 
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8BIT wrote:
I believe the DCDB input must be low for the receiver to work (check the datasheet) Not sure how your hardware is wired using the ftdi, it does not show the DCDB connection.

Daryl

Hmm, in the datasheet DCDB only fires up an interrupt. It doesn't block the receiver from reciving...

BigDumbDinosaur wrote:
You’ve got IRQB on your 65C22 wired directly to the MPU’s IRQB. The part number you list for the 65C22 is the ‘S’ version of the device, which has a totem-pole IRQ output. That will not work as expected, since the 65C22 will continuously drive IRQB high unless it is actually interrupting. If a device with an open-collector IRQ output interrupts—the 6551 falls into that category—it will attempt to sink the 65C22’s IRQ output. You should be able to surmise what will likely happen.

I am aware of this. The schematics label is wrong. I ordered a N version for this, which has an IRQ OC output. But i have found a bug in the library design i used for the 6551. DRDB and VCC are mixed up. So i corrected it on the PCB (with some wires... :-)) and voila it's now running. Even without Grounding the DCDB signal.
Sometimes it misses some chars, but that is mainly because of the LCD SPI bitbanging. I think with an interrupt routine using a buffer it will be better.
Thanks all for the help.
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GARTHWILSON
PostPosted: Tue Nov 01, 2022 8:44 am 
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Other manufacturers' data sheets say DCD\ must be low for the receiver to operate; but I'm not seeing that in the WDC data sheet. I don't have any WDC ones either.

willie68 wrote:
8BIT wrote:
I believe the DCDB input must be low for the receiver to work (check the datasheet) Not sure how your hardware is wired using the ftdi, it does not show the DCDB connection.

Daryl

Hmm, in the datasheet DCDB only fires up an interrupt. It doesn't block the receiver from reciving...

BigDumbDinosaur wrote:
You’ve got IRQB on your 65C22 wired directly to the MPU’s IRQB. The part number you list for the 65C22 is the ‘S’ version of the device, which has a totem-pole IRQ output. That will not work as expected, since the 65C22 will continuously drive IRQB high unless it is actually interrupting. If a device with an open-collector IRQ output interrupts—the 6551 falls into that category—it will attempt to sink the 65C22’s IRQ output. You should be able to surmise what will likely happen.

I am aware of this. The schematics label is wrong. I ordered a N version for this, which has an IRQ OC output.

Note that there are more differences than that. The S version also has:

  • much greater output drive strength
  • very high-impedance true CMOS inputs
  • hold devices on inputs, such that if an input stops being driven, it will maintain the last driven logic state

If you can put a Schottky diode in series with its IRQ\ output, or use an AND gate to combine IRQ\'s, I would strongly recommend the S version over the N version.

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