Like Garth, I cannot view that page. You can attach schematics, pictures, etc., to your posts here and save readers the trouble of having to go off-site.

Ah! A schematic that is actually a schematic and, especially important to me, is not in color.

74AHC is a good choice, as it combines the speed of 74AC with the more “gentle” outputs of 74HC. I've used 74AC/ACT in all my designs to date without noise problems, but these are on four-layer boards with internal ground and power planes, and meticulous attention to layout details. 74AC/ACT on a two-layer board may be a pretty unforgiving arrangement due to ground bounce, ringing, etc.

Here’s the circuit for my POC V1.3 design, which is all discrete logic and runs at 16 MHz. You might find something useful in it.

Having as less as possible AC/ACT chips on a breadboard is the way to go. On a PCB I would say it is fine if you have proper signal return paths / ground planes. Can you share screenshots of your PCB routing?

For the RAM, go with a slow, 55ns one before attempting to increase the speed. This goes for all the components, if they don't have a reason to be fast, go with slow chips, as they will be easier to manage for a start. Once you have a working slow build, then you can try to increase speed.

Your GAL can also be an issue with fast edges. Which model are you using? Can you also share how you're programming it and with which equations?

I see the problem. The ground and VCC are narrow 10mil? traces. That definitely won't work with fast edge rate components. You'll need to identify all the ground and VCC and add multiple wires (small 30 gauge wirewrap wires are OK) to form a grid. Ground wire grid is more important than VCC grid. In fact, add a few wires, test and observe how things change; add more and test. You'll be amazed how important grounds are.
Bill

I see the problem. The ground and VCC are narrow 10mil? traces. That definitely won't work with fast edge rate components. You'll need to identify all the ground and VCC and add multiple wires (small 30 gauge wirewrap wires are OK) to form a grid. Ground wire grid is more important than VCC grid. In fact, add a few wires, test and observe how things change; add more and test. You'll be amazed how important grounds are.
Bill

I see the problem. The ground and VCC are narrow 10mil? traces. That definitely won't work with fast edge rate components. You'll need to identify all the ground and VCC and add multiple wires (small 30 gauge wirewrap wires are OK) to form a grid. Ground wire grid is more important than VCC grid. In fact, add a few wires, test and observe how things change; add more and test. You'll be amazed how important grounds are.

Grid, yes. Definitely. The finer, the better. Trace width for ground and Vcc connections makes almost no difference though. See viewtopic.php?p=90824#p90824 .

Lesson learned... always have inner GND and VCC planes. I'll get my bodge wire out tomorrow and start soldering!

Lesson learned... always have inner GND and VCC planes. I'll get my bodge wire out tomorrow and start soldering!

I think what we're talking about here is output edge rate, rather than access time. They're two separate things. Without looking through a lot of data sheets again, I don't remember ever seeing the output edge rates specified on SRAMs. Have you?

Why? The RAM's speed has nothing to do with circuit performance, unless the RAM is too slow. With most SRAM, output transition rate has little relation to the speed rating.

No pullup resistor is required on RWB, as that output is driven in both directions—it's not an open-collector output.[/color]

No sir!

VDA and/or VPA is/are asserted midway during Ø2 low. At that time, the 816 will drive the data bus with the bank bits. Just how would using either/both of those signals to qualify read/write be helpful?

Asserting /RD during Ø2 low will cause severe data bus contention, making the system unstable at best, and DOA at worst. Asserting /WD during Ø2 low will create an opportunity for a wild write due to insufficient address bus setup time. During a write cycle, RWB goes low (according to the timing diagram) when VDA and/or VPA is/are asserted. However, that doesn't mean the rest of the hardware has “settled” following address bus setup. Also, asserting /WD before the rise of the clock means you are momentarily writing the bank bits to the addressed device, which is probably not a good idea.

Either reading and writing must be qualified with Ø2 or in lieu of such qualification, a bus transceiver must be used to isolate RAM, ROM and I/O hardware from the data bus whilst Ø2 is low. The “ideal” configuration is qualification with Ø2, along with a bus transceiver to deal with a small window of opportunity for contention to occur as the 816 “turns around” the data bus during a read cycle.

Caveat: nothing going to 65xx peripherals, e.g., 65C22, should be qualified by Ø2. Those devices “understand” the 65xx bus cycle and won't try to read or write during Ø2 low. In an 816 system, use of (as a minimum) VDA to qualify addresses to 65xx silicon is sufficient to avoid timing contretemps. Absolutely do not qualify addresses with Ø2. You’ll be disappointed with the results.

We must be looking at a different datasheet. TI's one here https://www.ti.com/lit/ds/symlink/cd74hc573.pdf specifies 10ns for the hold time over temperature at 5V. It could work if your LE signal is directly taken from a clock flip-flop and you have no additional logic for it (ie you don't use RDY)

It is useful if you use Bus Enable as this pin is tri-stated, but not required.