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GARTHWILSON

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 7:02 pm

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8428
Location: Southern California

sburrow wrote:

Does the 6522 VIA R/W input need to be qualified with Phi2? I know we have discussed that for RAM (and ROM), but does the VIA also need that same qualification? Would it hurt to use that same line for RAM, ROM, and VIA?

No. You must not qualify the VIA's R/W with phase 2. It has to be valid and stable before phase 2 rises.

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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BigDumbDinosaur

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 7:40 pm

Joined: Thu May 28, 2009 9:46 pm
Posts: 8155
Location: Midwestern USA

sburrow wrote:

I know I mentioned this to you before, but will reiterate.

Inputs to 65xx peripherals must not be qualified by Ø2. All inputs must be valid before the rise of the clock. That includes the address inputs and chip selects.

So, yes, you will feel pain if you try to control the 65C22 with with the signals used to control reading and writing of the RAM, ROM and non-65xx I/O devices.

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sburrow

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 7:43 pm

Joined: Sat Oct 09, 2021 11:21 am
Posts: 703
Location: Texas

Excellent, thank you all for reminding me about this.

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sburrow

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 8:00 pm

Joined: Sat Oct 09, 2021 11:21 am
Posts: 703
Location: Texas

Since I'm asking weird, questions, I might as well ask another.

How many decoupling capacitors are recommended? Why at 0.1 uF in particular? BDD, on your 65816 schematics, you use almost 20 of them. Then you also use 2 polarized capacitors, and those are at 100 uF and 0.1 uF. I was reading about your design, and you and others have said that a 4-layer PCB helps in this as well. Garth, you have one polarized 100 uF, and then one unpolarized 0.01 uF at each IC. Any particular reasons why those values and that amount of them? Does clock speed have any relation to capacitor value and count?

From what little experience I have, I can say that I have not been using these on my small breadboard test circuits. I am actually using a USB phone charger and it has a fairly consistent 5.1 V. I've also been using a LM1117-3.3V to create "logic high" values for some 74LS' chips. I haven't seen any issues, but this is very small time testing here.

Thank you, sorry if my questions are still so newbie. Feel free to ignore them at any time if you so desire.

Chad

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GARTHWILSON

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 8:26 pm

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8428
Location: Southern California

The bypass capacitor value is not critical. For years I was going with the lower .01uF value (instead of .1uF) because in a smaller package, you could get slightly lower inductance, and the self-resonant frequency would be higher too, particularly if it's leaded, since leads add unwanted inductance, somewhere around 20nH per inch. Recent years' capacitor development have however gotten us more and more capacitance in smaller and smaller packages. The bypass capacitor is kind of like the toilet tank. The water coming in from the wall doesn't come fast enough to get a good flush, but it fills the tank in time before the next flush. The tank can deliver two or three gallons in a couple of seconds. In the digital IC, if you had eight outputs that switch all at once, and if the parasitic capacitance load averaged out to 20pF, meaning 160pF for all eight, you can see that a .01uF (10,000pF) reserve would charge them all up with a negligible change in the power supply voltage across the IC. So .01uF should be totally fine. Would .1uF be better, if all other factors remain the same? Well, theoretically, although the improvement would be negligible. (See viewtopic.php?p=55450#p55450 however for why the bypass capacitors can only do so much, and will not fix every groundbounce-producing board-layout mistake.)

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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sburrow

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 9:27 pm

Joined: Sat Oct 09, 2021 11:21 am
Posts: 703
Location: Texas

Garth, now I'm learning about Ground Bounce. Learning something new every day!

I followed that link, read it, and that completely surprises me! I had never thought of having the VCC and GND both bounce together before, wow!

Following the links on that link, I was reading a bit of the summary for preventatives of this Ground Bounce. Here are few I found interesting:

- Use multi-layer boards with VDD and ground planes, with the device power pins soldered directly to the planes, to insure the lowest power line impedances possible.
- Use decoupling capacitors for every device, usually 0.10μF should be adequate. These capacitors should be located as close to the ground pin as possible.
- Avoid using sockets or wirewrap boards.

Garth, I know you are a fan of the wirewrap. I found this interesting.

The toilet analogy is perfect. And your description on that link was clear as well.

This Ground Bounce does seem to be less of an issue at lower speeds, if I am reading between the lines correctly. I don't know what "lower speeds" are, because 1 MHz is screaming fast in my mind.

Yet, I still don't feel I got a perfect "just do this" answer. And maybe there isn't one. But I have learned more about capacitors, and now Ground Bounce. Thank you for that! And thank you for your time with me.

Chad

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GARTHWILSON

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 9:55 pm

Joined: Fri Aug 30, 2002 1:09 am
Posts: 8428
Location: Southern California

sburrow wrote:

- Use decoupling capacitors for every device, usually 0.10μF should be adequate. These capacitors should be located as close to the ground pin as possible.

If the only plane you had were a ground plane, you'd want the ground pin of the IC to go directly to the plane, and the bypass capacitor going from the VDD pin to the ground plane with the shortest connections possible, right at the VDD pin, not the ground pin.

Quote:

- Avoid using sockets or wirewrap boards.

Garth, I know you are a fan of the wirewrap. I found this interesting.

Custom PCBs' prices have come way down, such that now the hobbyist can afford to get his own made. The best AC performance will be had with SMT components on a well designed PCB. I believe there's still a (limited) place for wire-wrap though; and if wirewrap is done correctly, it will be way, way, way better than other non-PCB construction methods, especially solderless breadboards. You can get perfboard for your WW creation with a ground plane, or even planes on both sides, and the wires can potentially be considerably shorter than the connections on a PCB, going diagonally and straight to their destination, and hugging the ground plane.

Quote:

This Ground Bounce does seem to be less of an issue at lower speeds, if I am reading between the lines correctly. I don't know what "lower speeds" are, because 1 MHz is screaming fast in my mind.

Again, it's not about MHz. It's about the edge rates, ie, how fast an output transitions from a 0 to a 1 or vice-versa. Jack Ganssle's YouTube video, "I Only Probed the Board With a Scope - Why Did My Board Crash?," the part from about 2:20 to 3:00, graphically shows on a high-end oscilloscope that the ugly ringing remains unaffected as he turns the clock frequency up and down. There is some grace in the fact that turning the clock speed down gives more time for address- and data-bus ringing to die out before the next clock edge; but you still have to keep your nose clean regarding the clock circuit, since if the ringing or groundbounce is bad enough there, the processor and various other devices might see it as multiple clock edges they're supposed to act on but can't handle that fast.

However, slow parts like 2MHz processors and 74HCxx logic have slow enough edge rates that you can get away with murder, and if things are schematically correct, they'll work with some pretty bad construction. The faster parts, including 74ACxx logic, won't be so forgiving. Many users will, by luck, get their creation working, while others will have problems which they won't understand and be able to fix.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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sburrow

Post subject: Re: Single 6522 for a few applications

Posted: Wed Oct 20, 2021 10:46 pm

Joined: Sat Oct 09, 2021 11:21 am
Posts: 703
Location: Texas

GARTHWILSON wrote:

Again, it's not about MHz. It's about the edge rates, ie, how fast an output transitions from a 0 to a 1 or vice-versa.

However, slow parts like 2MHz processors and 74HCxx logic have slow enough edge rates that you can get away with murder, and if things are schematically correct, they'll work with some pretty bad construction. The faster parts, including 74ACxx logic, won't be so forgiving. Many users will, by luck, get their creation working, while others will have problems which they won't understand and be able to fix.

Ah ha! NOW that is making sense. And that video was exactly making that point. I gotcha now.

Garth, thank you for your help and your patience with me.

Chad

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BigDumbDinosaur

Post subject: Re: Single 6522 for a few applications

Posted: Thu Oct 21, 2021 1:40 am

Joined: Thu May 28, 2009 9:46 pm
Posts: 8155
Location: Midwestern USA

sburrow wrote:

BDD, on your 65816 schematics, you use almost 20 of them. Then you also use 2 polarized capacitors, and those are at 100 uF and 0.1 uF.

Every device has a 0.1 uF bypass capacitor. Also, one is placed at the power connector to keep circuit noise from sneaking out the back door and causing RFI. Another is placed by a header that can be configured to power an external terminal adapter. That's why you see so many of them. Bypass capacitors are like money: no such thing as "too much."

The electrolytics add extra oomph to VCC when many devices simultaneously switch. I place one electrolytic at the power input and the other close by the MAX238 (or MAX248) transceiver, as the latter are current-hungry during TIA-232 I/O activity. See Garth's toilet tank analogy.

Quote:

Following the links on that link, I was reading a bit of the summary for preventatives of this Ground Bounce. Here are few I found interesting:

- Use multi-layer boards with VDD and ground planes, with the device power pins soldered directly to the planes, to insure the lowest power line impedances possible.

Using a four-layer board is definitely a good thing, especially if the system is expected to run at high speeds. Having those inner ground and power planes confers a number of advantages, not the least of which is your layout density can be greater because you don't have to make room for VCC and ground traces. Greater density reduces signal trace lengths, which helps to avoid transmission line effects and other maladies that may make the unit unstable or DOA.

That said, people have built high-speed units on two-layer boards. And as you should know, you can usually get away with murder at 1 MHz. For a first effort, I'd suggest you do it in two-layers to gain design skills with component placement and circuit routing.

Quote:

- Use decoupling capacitors for every device, usually 0.10μF should be adequate. These capacitors should be located as close to the ground pin as possible.

Yes, 0.1μF is good—that's what I use. However, not all capacitors are created equal and as Garth explained, lead inductance and self-resonant characteristics get into the picture and can work against what the capacitor is supposed to be doing. Also important to consider is how the capacitor behaves when voltage is applied and as operating temperature changes.

A common misconception is the criticality of bypassing is directly related to clock speed. It isn't. The factor that should be considered first is the switching speed of the device's outputs and the related effects on the VCC and ground paths. Modern logic families' outputs have very fast edges, with 74ABT and 74AC going well down into the single-digit nanosecond range. Those extremely fast edges carry strong harmonic content that can extend into the gigahertz range, regardless of how often the outputs change state.

Correspondingly, as an output makes a transition from one state to the other there is a very brief but strong current transient being drawn by the device, the rate and amplitude of the transient being tied to the edge rate of the output making the transition, as well as the magnitude of the load being driven. That transient produces very high frequency harmonics that are injected into the VCC circuit and to a lesser extent, the ground circuit.

The bypass capacitors are there to bypass the harmonics produce by switching transients to ground, as well as to momentarily supply extra current to the device as it switches. Therefore, bypass capacitors have to be chosen with switching speed in mind, not clock rate. For bypass work, X7R MLCC capacitors rated at 50 volts are a good choice. Yes, that voltage rating is way higher than the circuit's operating voltage, but it accounts for the fact that an MLCC's capacitance tends to decrease as applied voltage increases.

Bypass capacitors should be physically located as close to the device's VCC pin as possible. If building on a two-layer board, the VCC and ground traces to the capacitor should be as short and direct as possible to minimize inductance. Also, use capacitors with 0.1" lead spacing (or smaller, if you can manage it) to reduce the amount of lead between the capacitor and its connection points in the circuit.

If building on a four-layer board, i.e., one with internal ground and power planes (which is what I use with my POC units), the bypass capacitor should be directly connected to both power planes. The ground pin of the associated device should be directly connected to the ground plane. The device's VCC pin should be connected by a short and relatively wide trace to the VCC side of the capacitor, and not directly to the inner power plane. The reason for doing so is the capacitor will do a better job of sucking up switching noise.

Quote:

- Avoid using sockets or wirewrap boards.

Garth, I know you are a fan of the wirewrap. I found this interesting.

There's nothing wrong with wirewrap—hobbyists have built wirewrapped units that can run quite fast. However, as Garth noted, PCBs have become inexpensive and are, of course, less tedious and error-prone to work with than a wirewrapped unit. Wirewrap does have the advantage of being easily "correctible" if you make a design or assembly error. Fixing a mistake with a PCB usually means getting out the X-Acto knife and bodge wire. :shock:

My first POC unit underwent such surgery to solve a logic problem.

As for sockets, best to avoid them if possible. They add parasitic capacitance, inductance and cost to the system, and create a possible failure point. I only use them for "expensive" parts that I might want to salvage for a new unit.

Quote:

This Ground Bounce does seem to be less of an issue at lower speeds, if I am reading between the lines correctly. I don't know what "lower speeds" are, because 1 MHz is screaming fast in my mind.

The bad effects of ground bounce can get you at low speeds. However, with low speeds, things have more time to settle down, so mild cases of ground bounce are often tolerable. Be that as it may, you really need to avoid ground bounce problems. Good construction techniques always help.

_________________
x86? We ain't got no x86. We don't NEED no stinking x86!

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sburrow

Post subject: Re: Single 6522 for a few applications

Posted: Thu Oct 21, 2021 2:13 am

Joined: Sat Oct 09, 2021 11:21 am
Posts: 703
Location: Texas

BigDumbDinosaur wrote:

So let me understand your schematic correctly then:

http://sbc.bcstechnology.net/images/sbc_v1_page04.gif

At the bottom left corner, you have a BUNCH of capacitors all in a row. What you are implying is that there is one capacitor there for each component, and that it's placed at the VCC side of that component? You are not using some 20x capacitor array network or something?

BigDumbDinosaur wrote:

For a first effort, I'd suggest you do it in two-layers to gain design skills with component placement and circuit routing.

I've been thinking of a 2-layer design for a while. I don't know trace sizes very well, I know they are dependent on amps and all that, but there are numerous factors at play. My logic lines always seem too small, and my power lines always seem too big. With that in mind, what if I were to make a 2-layer board, but knowing that I will connect all VCC and GND pins with wires on the bottom. Like how you had to perform 'surgery' on your board, but knowing that I will be doing that going into it. Would that help with sizing? With something like that, could I more easily fit some decoupling capacitors in there? It's probably a dumb idea, but I think I need someone to tell me that before I really believe it.

BigDumbDinosaur wrote:

The device's VCC pin should be connected by a short and relatively wide trace to the VCC side of the capacitor, and not directly to the inner power plane.

Hm! That is interesting, thank you for that tip. Hadn't heard that before.

BDD, thank you for that excellent and detailed response. Thank you for teaching me so much about this.

Chad

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BigDumbDinosaur

Post subject: Re: Single 6522 for a few applications

Posted: Thu Oct 21, 2021 6:45 am

Joined: Thu May 28, 2009 9:46 pm
Posts: 8155
Location: Midwestern USA

sburrow wrote:

Each capacitor is a "stand-alone" part. It is essential that a bypass capacitor be as physically close as possible to the VCC pin of the device that it bypasses to minimize inductance. That can't be done with a capacitor array.

The schematic you were looking at is of the very first POC unit. In newer schematics, I "distribute" the bypass capacitors so they are on the same page as the devices they bypass. The below schematic of POC V1.2 illustrates this change. Also, most of the bypass capacitors have the same numeric designation as the corresponding device. So C5 bypasses U5.

Attachment:

File comment: POC V1.2 Schematic

poc12.pdf [308.41 KiB]
Downloaded 37 times

The above also illustrates some "good practices" in drawing schematics. such as using logic symbols for gates instead of black boxes, using netlist symbols as a means to "bridge" circuits from page-to-page and not to connect things on the same page, and being reasonably concise in notations and component identifications. I try to draw my schematics in a way that would allow anyone skilled in the art to build the unit and get it running.

Quote:

I've been thinking of a 2-layer design for a while. I don't know trace sizes very well, I know they are dependent on amps and all that, but there are numerous factors at play.

Signal traces can be quite narrow. I use 0.006" traces for signals. Power-handling traces are wider, of course. In a typical 65C02 computer design, nothing draws all that much current, so you don't need big, honkin' power-handling traces (more on this below). Take a look at the illustration for POC V1.2's PCB below to get some ideas.

Attachment:

File comment: POC V1.2 PCB Layout

poc_v1.2_pcb.gif [ 98.38 KiB | Viewed 4620 times ]

Red traces are on top and green on the bottom. This is actually a four-layer board, and is stable at 20 MHz. It was the last unit I built with PDIP logic devices.

Quote:

With that in mind, what if I were to make a 2-layer board, but knowing that I will connect all VCC and GND pins with wires on the bottom.

I would not do that. There's not any value in using actual wire for VCC and ground, and you may inadvertently create some significant problems by doing so. Do it all in traces and save yourself some later troubleshooting aggravation.

What is typically done on two-layer PCBs is to run the VCC and ground traces on opposite sides of the board. In my designs, I go north-south on top and east-west on the bottom, as seen in the above illustration (which, incidentally, has an amusing layout error in it). Traces are also run at angles on both sides as necessary to shorten signal paths and dodge obstacles, such as mounting holes.

After you approximately determine where you are going to place your chips you lay out a grid for VCC and ground so you don't have to run traces too far from each grid to the relevant pins on the chips. While doing that, also place your bypass capacitors to get them close in to the chips' VCC pins. I generally advise beginners to do the power and ground distribution first, since those will be wider traces and hence have somewhat-less routing "flexibility." Once power and ground have been distributed you can start "wiring" your circuits.

A good width for the VCC and ground grid traces is 0.050"-0.060". Here, size will matter, as you absolutely don't want any possibility of voltage drop in the power distribution grid. Although CMOS logic draws a minuscule amount of current when it's idle, significant draw occurs as output states change. With much of the system orchestrated by the Ø2 clock, many such state changes may simultaneously occur, with an attendant momentary and very-abrupt increase in power draw.

Where traces branch off the power distribution grid to individual chips you can use a trace width equal to or slightly smaller than the pad diameter to which it will connect. If the path has to change layers, use a via at least one size larger than the trace width.

Turning back to signal traces, I wouldn't go any larger than 0.010" width and if your PCB drafting software will allow it, go smaller. Doing so will make routing easier. Commensurate with the small size of signal traces, you use small via to transfer a circuit from one layer to the other. The current in signal traces is rarely more than a few mils, so you can go very small.

One other thing. Devices that are connected to each other should, if possible, be mounted next to each other. Initially allow plenty of space between devices. You can close it up once you've got a routing done. Needless to say, meticulousness is essential.

Hope this helps you a bit.

_________________
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sburrow

Post subject: Re: Single 6522 for a few applications

Posted: Thu Oct 21, 2021 10:36 am

Joined: Sat Oct 09, 2021 11:21 am
Posts: 703
Location: Texas

BigDumbDinosaur wrote:

Hope this helps you a bit.

It does quite a bit actually! You answered questions I wasn't even asking yet, so that was very helpful.

I will re-read it and send another message back soon, but I gotta run to work now.

Thank you again BDD, I appreciate this very much.

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Dr Jefyll

Post subject: Re: Single 6522 for a few applications

Posted: Thu Oct 21, 2021 12:53 pm

Joined: Fri Dec 11, 2009 3:50 pm
Posts: 3349
Location: Ontario, Canada

sburrow wrote:

what if I were to make a 2-layer board, but knowing that I will connect all VCC and GND pins with wires on the bottom

Not a great idea -- at least not for all VCC and GND, as you say. Things would get rather cluttered. But wires on the bottom (or top) can be a tidy solution if all you're doing is making a short hop here and there. (In fact, that's the reason zero-ohm SMT "resistors" are available. They allow one trace to jump over another.

)

-- Jeff

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sburrow

Post subject: Re: Single 6522 for a few applications

Posted: Thu Oct 21, 2021 1:33 pm

Joined: Sat Oct 09, 2021 11:21 am
Posts: 703
Location: Texas

Dr Jefyll wrote:

In fact, that's the reason zero-ohm SMT "resistors" are available. They allow one trace to jump over another.

Ha! That makes a lot of sense! It kind of adds a 3rd layer (or 4th) layer to a typical 2 layer board. Gotcha, thank you for that. I have been wondering about that for a while.

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plasmo

Post subject: Re: Single 6522 for a few applications

Posted: Thu Oct 21, 2021 2:18 pm

Joined: Fri Dec 21, 2018 1:05 am
Posts: 1076
Location: Albuquerque NM USA

Chad,
I think you are quite young and still have good eyes and nimble hands, so don't be afraid to hand wire your design. A hybrid of printed pc board for address/data buses and handwire for control logic is a reasonable approach. As many had already said, good ground is very important, yet not so important to require 4-layer pc board. All my retro designs in last 3-4 years were 2-layer pc boards and autorouted, but I always manually routed an extra ring of wide ground/VCC traces to provide additional signal return. Here is an example of hybrid PCB and handwired design; 2-layer prototype board with existing routes, point-to-point manual wiring for added logic. No problem running W65C02 up to 25.175MHz although it nominally run at 14.7MHz.
Bill

Attachments:

DSC_64450213.jpg [ 1.42 MiB | Viewed 4579 times ]

DSC_64470213.jpg [ 1.29 MiB | Viewed 4579 times ]

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