That addressing mode doesn't exist on the 6502. (At least, not in the NMOS version that the 2600 uses. Maybe they added it to some 65C02 variants.)

I find this reference useful for quickly looking up the addressing modes available for each instruction. (And what flags are set by each instruction, too.)

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Curt J. Sampson - github.com/0cjs

I imagine it's because the NMOS 6502 core - which is what you'd get in a 2600 - doesn't have a non-indexed indirect addressing mode. You either get pre-indexed by X, or post-indexed by Y.

The approach by sark02 looks sound in principle, taking advantage of the index registers and the post-indexed addressing mode. I don't have time today to fettle the setup code around it, but the core is useful. Its one limitation is that it doesn't easily support a final inner loop of less than 256 bytes; you have to put the remainder portion in the first iteration. This may not matter in the end, though.

Okay, did some study on the responses, and thank you both for taking the time. I did leave the parenthesis in and may have conflated things a touch ...

So why not the use zero page addressing mode: sta scrLow ? scrLow is only a byte value, so will still refer to page 0. There should be little change, except for saving a few cycles using the zero page mode.

like:


Still trying to wrap my head around this, so pleae be patient...

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Bill

A quick addendum to my code:
Whereas sta (ind),y is 6 cycles, std abs,y is only 5, so if the loop can be in RAM rather than ROM, it can be modified to:This uses (L1+2,L1+1) as the write address, as opposed to ($21,$20). Saves 1 cycle/iteration.

I don't know if it's just the kooky way my brain works, but I think you can save some code space but get 'er done just as quickly if your application can tolerate filling from high to low (untested):

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

Your brain works like a 6502! I guess that qualifies as "kooky...."

And yes, I've noticed this too. My bigint representation was initially little-endian, following the convention of the CPU. But I changed it to big-endian, going opposite the convention, specifically because on the 6502 you can save a CMP and perhaps more by counting down to zero rather than counting up to your target. A related technique is to use 1-based indexes for arrays rather than 0-based: the loop control is just DEY followed by BEQ done.

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Curt J. Sampson - github.com/0cjs

Nice one.