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PostPosted: Fri Jan 03, 2020 8:21 am 
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I'm following along with Ben Eater's 6502 project (ergo, I'm a newb), and all has gone pretty well until I hit a weird snag.

The breadboard-based setup has no RAM, just an EEPROM for code. And it outputs via a 6522. The first stage of the project had the computer blinking LEDs. I got that working, and even experimented somewhat with the code, with success.

The setup also involves using an Arduino Mega as a poor man's logic analyser. It monitors the 16 address lines, the 8 data lines, the RWB signal and the PHI2 clock, which it uses to trigger an interrupt prompting it to read. It then prints the state of the address and data buses, plus the RWB line, on the serial monitor.

And I need to stress that this has all been working fine.

But then the next stage was replacing the LEDs with a 16x2 LCD display. This involves only changes to the output side of the 6522. Everything to do with the 6502 and EEPROM remained the same.

The code runs fine, inasmuch as the relevant addresses and data values are appearing on the buses - when it comes to reading from the EEPROM. But when the time comes for the 6502 to write a value to the data bus, it's always 0!

Here's some sample output from the serial monitor on the Arduino. Each line, from the left, shows: ADDR bus in binary; DATA bus in binary, ADDR bus in hex; state of RWB pin; DATA bus in hex. The comments I've added later.

Code:
1111111111111100   00000000  fffc  r 00
1111111111111101   10000000  fffd  r 80
1000000000000000   10101001  8000  r a9    ; lda #$ff
1000000000000001   11111111  8001  r ff
1000000000000010   10001101  8002  r 8d    ; sta $6002
1000000000000011   00000010  8003  r 02
1000000000000100   01100000  8004  r 60
0110000000000010   00000000  6002  W 00    ; so why is it writing 0??
1000000000000101   10101001  8005  r a9    ; lda #$e0
1000000000000110   11100000  8006  r e0
1000000000000111   10001101  8007  r 8d    ; sta $6003
1000000000001000   00000011  8008  r 03
1000000000001001   01100000  8009  r 60
0110000000000011   00000000  6003  W 00    ; writing 0 again!
1000000000001010   10101001  800a  r a9    ; lda #$38
1000000000001011   00111000  800b  r 38
1000000000001100   10001101  800c  r 8d    ; sta $6000
1000000000001101   00000000  800d  r 00
1000000000001110   01100000  800e  r 60
0110000000000000   00000000  6000  W 00    ; yup, 0 again


There's a lot more of this sort of thing, but the result of every call to STA is 0 on the data bus. The 'r' and 'W' flags show that the RWB pin is in the correct state. And the opcodes and operands in the EEPROM are being loaded on to the data bus okay. Also, the PC appears to be operating normally, in that the addresses increment as you'd expect. I just don't understand why the 6502 appears not to be putting anything onto the data bus in write mode.

The machine is being run at 1Hz (yup, that slow) with a Rigol function gen as a clock source.

As a check, I reflashed the EEPROM with the code that had previously been working fine. With nothing having changed in the code, it too is now seeing only 0 on all writes.

I swear I've changed nothing other than the display (I tried removing that, too). Of course, this being a breadboard system, it's entirely possible I've accidentally nudged something.

I plan to hook up the scope to start checking signal levels where I can. But any ideas what sort of thing might cause this problem would be welcome.

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PostPosted: Fri Jan 03, 2020 8:41 am 
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Maybe something is holding the data lines low for some reason. Double check that the EEPROM is not enabled when you're trying to address the 6522. Maybe put another line from your arduino to that enable pin for the ROM, and read it each cycle, and output it to the screen along with the rest of it. That way you can see the state of the ROM enable pin for each of those cycles. If the EEPROM is still enabled for some reason when you are trying to write to the 6522 addresses, and the EEPROM was has zeros in those addresses, it would probably hold the lines low. This would probably point to something wrong with the decoding logic.


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PostPosted: Fri Jan 03, 2020 8:55 am 
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That's a good idea - I'll give that a go tonight, thanks.

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PostPosted: Fri Jan 03, 2020 9:05 am 
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You might check also where the data bus is getting sampled relative to the rising and falling edges of phase 2. WDC's pin drivers are very, very strong—able to pull even up to 4.2V with 19mA. If they're trying to pull a line up and you short it to ground, it will give you about 50mA per pin, according to my experiments.

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PostPosted: Fri Jan 03, 2020 9:08 am 
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Turns out, I couldn't wait until tonight. I traced back from the /CE pin on the EEPROM, which has a wire running to the decoder chip. Aaaand... it was connected to ground! Clearly, at some point that wire had become disconnected and I've stuffed it back in without even thinking about it. And it was two rows along from where it should have been. So you were right... the EEPROM was permanently enabled.

Thanks for the tip.

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PostPosted: Fri Jan 03, 2020 9:12 am 
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I'm glad we found the solution!
Happy Computing!


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PostPosted: Fri Jan 03, 2020 3:16 pm 
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speculatrix wrote:
the EEPROM was permanently enabled.

speculatrix, I'm curious what type of 6502 you are using. I'm guessing it's an NMOS one. Or, if it's CMOS (ie, a 65C02) then it's from Rockwell or similar -- not WDC.

As Garth noted, WDC's pin drivers are very, very strong. But in your case the EEPROM was able to overpower the CPU.

-- Jeff

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PostPosted: Fri Jan 03, 2020 3:23 pm 
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I was using the term '6502' generically. It is indeed a 65C02.

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PostPosted: Fri Jan 03, 2020 9:00 pm 
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There's another question raised, although it's a moot point now.

I PM'd speculatrix and we determined that the CPU *is* a WDC device. Based on what Garth said about the high drive capability of modern WDC CPU's, I find it highly doubtful that the EEPROM was able to overpower it. So, how to explain the fact the logic anaylser was reading zeroes during the cycles which had contention? I'm inclined to think the contention momentarily pulled the 5 Volt supply far below spec, and whatever voltage remained on the data bus pins was low enough to be seen by the LA as zeros. Or maybe someone can suggest a better theory...? It does seem like a bit of a headscratcher! :o

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PostPosted: Fri Jan 03, 2020 10:19 pm 
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The ROM doesn't need to pull the line all the way down to 0 volts. It only needs to pull it below the threshold to be considered logic zero. It doesn't have to pull all the way to ground. The the cpu has a certain resistance to 5 volts when its set to output 1. And the ROM has a certain resistance to ground when its told to output to 0. This is a voltage divider, and the ratio of those resistances is going to determine the outcome. The magnitude of the resistances will determine the current. This is of course a very simplified way to look at it. The devices use transistors on the outputs, not simple resistors, but they still have an impedance, or resistance through them. You can't simply say that the W65C02 is capable of pulling the sun into the earth without also considering the traits of the sun. There's more than one device in the circuit. You must consider the ROM as well.

Edit: So if we add in what Garth told us about the high drive capability of the WDC 65C02, that probably means it has a pretty low resistance to 5 volts when it is switched on to a logic output of 1, and a low resistance to ground when outputting a 0. This would allow it to source or sink more current without heating up, drive longer lines and push pins set up as inputs around a bit easier even when conditions are not ideal. But this would put the the WDC in a disadvantage when in a battle of the outputs like this with a device that has a higher resistance that is driving the line as an output.

attached is a very rough sketch


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PostPosted: Fri Jan 03, 2020 10:54 pm 
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Dr Jefyll wrote:
So, how to explain the fact the logic anaylser was reading zeroes during the cycles which had contention?
Perhaps a ... "budget minded" logic analyzer, or one not configured for the correct logic family? Well, actually, in this case it seemed to get it right. Not to be too oxymoronic, but CMOS is generally not all that tolerant of low highs.

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PostPosted: Fri Jan 03, 2020 11:19 pm 
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Yes, thanks for elaborating, CaptainCulry. The two devices in contention create a voltage divider, and there'll be a non-zero voltage which is nevertheless reported as zero by the Logic Analyzer.
Dr Jefyll wrote:
whatever voltage remained on the data bus pins was low enough to be seen by the LA as zeros


At a more usual operating frequency (eg: 1 MHz), a single cycle of contention would be sufficiently brief that the power supply probably wouldn't collapse. But speculatrix mentioned running far more slowly, ie, 1 Hz... :|

... which, in light of his tag line -- "I like it when things smoke" -- almost seems like an attempt at wish fulfillment! :lol:

ps to BillO: good point about CMOS logic levels. These would "help" the LA to mis-report a low-ish voltage as being zero.

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PostPosted: Sat Jan 04, 2020 1:25 am 
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Quote:
This is a voltage divider, and the ratio of those resistances is going to determine the outcome. The magnitude of the resistances will determine the current. This is of course a very simplified way to look at it. The devices use transistors on the outputs, not simple resistors, but they still have an impedance, or resistance through them. You can't simply say that the W65C02 is capable of pulling the sun into the earth without also considering the traits of the sun. There's more than one device in the circuit. You must consider the ROM as well.

Yes; perhaps I should have said that what I measured was that the WDC parts could pull to within 0.8V of either rail at 19mA per pin, but there was a current limit of about 50mA when shorted to the opposite rail. I still need to go back and find the details to check on; but in any case, it's not just a resistor. The Rockwell 65c22 VIA OTOH was a little different. I could not pull up quite as hard, but it would give you 100mA (per pin) if you short a low output to Vcc!

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PostPosted: Sat Jan 04, 2020 7:29 pm 
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Can I just add that I'm glad my simple cock-up has provoked such an interesting debate. It's what I'm here for...

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PostPosted: Thu Apr 02, 2020 7:35 pm 
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CaptainCulry wrote:
But this would put the the WDC in a disadvantage when in a battle of the outputs like this with a device that has a higher resistance that is driving the line as an output.
attached is a very rough sketch

That sketch does not look correct to me. The formula for a voltage divider of the form
Code:
 +5V ---- R1 ---- Vout ---- R2 ---- GND
is
Code:
               R2
Vout = 5V * ---------
             R1 + R2
You seem to have the wrong term above the bar, you should have Rrom up there instead of Rcpu. The lower the CPU's internal "resistance" as compared that of the ROM, the higher the level at Vout will be. (And this makes sense when remembering that V=IR: the current is the same at all points on that line, so the bigger resistor must be dropping more voltage.)

That said, there's a lot else going on there that is not taken into account in this simple model. I would not be surprised if, though the WDC part can source a lot more current than the ROM, the ROM is capable of sinking considerably more current than it's sourcing, making the line asymmetrical such that whichever wants to pull it towards zero will "win." Further, both the 6522 and the the Amtel MCU on the Arduino are directly connected to that line as well, and thus they will also be sinking some current from the line (though I don't know how much difference that would make).

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