Not quite; the ninth bit of the result is N xor V.

Thanks, dclxvi. If V is clear then C is clearly not the ninth bit in the signed sense. But if V is set, is there a (signed) test case you can provide to us where C != N xor V ??

P.S. In other words, can you tell me if the following statements are true in the general case:

On the 65xx, the 8-bit twos complement result of the ADC and SBC instructions is contained in the accumulator, unless the V flag is set, in which case the 9-bit twos complement result is contained in the C flag appended to the most-significant edge of the accumulator. In the former case, the N flag contains the sign of the result, and in the latter case the C flag contains the sign. Also, the Z flag is invalid in the special 9-bit case of 1 00000000 (-256), but valid otherwise.

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

A few months ago I presented a 16 x 16 Signed Multiplication routine for my M65C02A core and Bitwise provided one for th 65816. Initial testing provided good results, but Bitwise indicated that he wasn't getting the expected result for a product of -32768 x -32768.

Some time ago I had decided to implement an arithmetic right shift instruction for my M65C02A core. The intention was to use it improve the time required for multiplications using the Booth algorithm. A previous attempt at a 8 x 8 signed multiplication routine for the 65C02 using a Booth algorithm required keeping a "guard" bit for the sign bit.

In my M65C02A core, I also implemented an instruction to reverse the bits of a register which allows the C flag / bit to function as the Booth "recoding" memory bit and the N flag to sense the state of the next bit in the multiplier. The multiplier is shifted left after reversing it which allows the C flag / bit to hold the previously shifted value and the N flag to test the state of the next multiplier bit. A simple SEC instruction at the beginning of the routine correctly initializes the Booth "recoding" memory bit.

Regardless, a guard bit is required for the sign bit of the product register. In an hardware implementation, an additional bit duplicating the sign bit is very easily included. Because of the number of additional instructions and memory cycles / locations required to implement a guard bit, I decided to use the overflow flag V to indicate those cases where the addition / subtraction of the multiplicand to the double length product register overflowed the representation. I restore the sign of the product during the arithmetic right shift as described below. In short, I think that the sign is determined from the N and V flags rather than the C and V flags:

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Michael A.

Holy moly, Batman! That thing is ginormous!

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Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

Thing of beauty isn't it?

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Michael A.

Just wanted to say thank you because I was having a hard time trying to understand the Overflow thing while having some fun with a customization of the Ben Eater 8 bit computer based on TTL chips (https://tomnisbet.github.io/nqsap/docs/flags/ linking to your 74181 with V_Flag and related pages, that I found very difficult to comprehend at the beginning, but now I'm so happy I managed to understand let's say 95%)