One common arrangement -- a typical system -- is when the processor sees RAM in the bottom 32K and ROM (or EPROM or EEPROM) in the top 32K.
A0-A14 (from the processor) would attach to A0-A14 of both the RAM and the ROM. And somehow (there are various ways of arranging this) A15 of the processor would, when low, activate the RAM (via its CE, OE and WE). Likewise, when A15 is high it would be ROM that gets activated instead.
Thus the RAM (whose own internal universe is just 32K) is only active when the processor outputs addresses 0 to $7FFF -- ie, addresses with A15 = 0. The ROM (also with an internal universe of only 32K) is active only when the processor outputs addresses $8000 to $FFFF -- ie, addresses with A15 = 1.
Your present arrangement lacks any connection from A15, and the ROM (because its CE and OE are always low) is active whether A15 is high or low. IOW, when the processor asks for the lower 32K it gets ROM, and when it asks for the upper 32K it gets ROM. The ROM is active in
both cases.
In this configuration you'll be able to do certain limited tests. For example, your loop should work. But it won't be long before you'll want some RAM (and I/O) attached!
Code:
loop: lda #$12
jmp loop
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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