Well, after failing to get my '816 doing a free run on a breadboard using discreet logic, you would think I would wise up and put the wire strippers down and the oscope in the closet and go outside to enjoy the good weather.

But no, I'm too dumb to know better, and too stubborn to admit defeat even when I am clearly over my head.

I decided to just hook the CPU up to the FPGA board and to start implementing all the glue logic required since I'm ultimately heading that way.

If you care to see it running just hit the link https://youtu.be/L1oqJR2sejY. I'm sure to most of you it will be pretty ho-hum, but hey, I'm excited! Some of us are easily amused.

Next up is adding some ROM/RAM and seeing if I can get it running something other than a NOP.

Thanks for all the info you guys have provided, it has been very helpful.

Well done! Interesting to see all the control signals when it's running so slowly.

Well I got address decoding working and I am now executing code from ROM and RAM. I am using some of the FPGA's internal memory resources to provide 8k of ROM at $00E000 and 8K of RAM at $000000. I am writing an JMP instruction to $000080 and then jumping to it to test out RAM accesses. I have address decoding working for the full 16Mb address including I/O at $00D000 - $00DFFF, and additional ROM at $A000- $BFFF. Nothing is hooked up at those addresses yet but decoding for all addresses is the same so things should work once I have something on the bus at those addresses.

Next up I think will be a simple serial device implemented on the FPGA.

Video link for those who are interested. https://www.youtube.com/watch?v=6nTkj9oNv4s