Table 4.2 in the current 65C816 data sheet list the cycle timings. The columns are arranged by max clock speed and voltage with the timings listed below. Are those timings relative to clock speed or the voltage?

For instance If the cpu is running at 3.3v and 8Mhz they list the BA0-BA7 setup time as 40ns and under the 1.8v and 2Mhz column they list it as 150ns.

What timing should I expect for say 2Mhz and 3.3v? 40ns or 150ns? I know that timing in CMOS 74xx logic is related to Vcc. Is the same true for the '816?

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Seconded: Jeff's explanations are well worth a read.

But the quick answer is that setup times depend on voltage. (Perhaps reason about it like this: they can't depend on clock speed because the previous clock edge was in the distant past, and the clock edge of interest is in the immediate future.)

You choose the voltage, and all the timings fall out from that, including the minimum clock period, which is to say the maximum clock speed. The table isn't well-designed, I think.

Absolutely awesome, exactly what I needed and then some. Thank you!