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PostPosted: Mon May 28, 2018 7:50 pm 
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cynlic wrote:
I think this question stems from my ignorance of some implementation details (I looked up a few data-sheets of various counters and was still confused) but if the phase accumulator is tied to the same Φ2 as the CPU, doesn't that clock-speed impact the lowest representable frequency? Taking Garth's example, using a 16bit accumulator to index into an 8bit memory address space, the slowest sample period is 1 sample per 256 16bit increments. But isn't the speed of that incrementation dependent upon the Φ2? It seems to me like you could easily overshoot and make it impossible to represent the lower frequency range. I assume that carefully adjusting the Φ2 and the number of bits used by the counter could result in something that’s “just right,” representing the necessary range of frequencies, but I don’t think that’s what everyone is saying should be done.

Correct. If you have, say, a 16-bit phase accumulator and it's clocked at 5 MHz, the slowest you can get is a roll-over every ~13ms, or about 76 Hz (about the second D#/Eb from the bottom on a piano.) There are two solutions to this: either add more bits to the accumulator (a 24-bit accumulator clocked at 5 MHz can go all the way down to 0.29 Hz,) or simply divide the master clock before sending it to the phase accumulator.

GARTHWILSON wrote:
There are more complicated things with although interesting, probably would not be addressed on a 6502-based synth, like the fact that with some instruments like flute and recorder, the color of the sound cycles with the pitch in vibrato, getting more airy and complex in the higher portion of the cycle. We also have not taken into account the attack sound for beginning notes on various instruments; but again that's getting pretty complicated, and if controlled by a keyboard, would definitely need one that senses how quickly the key went down, or some variation on that theme.

Yeah, that's more advanced stuff for sure. Though you could make a start if the voices had individual lowpass filters by using a base waveform with the brighter, more complex harmonic content and varying the filter cutoff along with the pitch in the vibrato. Attack transients are where it gets really complex, and in several synthesizers of the '80s (f'rexample the Ensoniq SQ-80 and Roland's entire "Linear Arithmetic" line, starting with the D-50) they just cut to the chase and used sampled attack transients coupled with synthesized waveforms or simpler looped samples plus filtering for the body of the note. Worked surprisingly well, though it was nothing you'd ever mistake for the real thing.


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PostPosted: Sun Jun 03, 2018 3:49 pm 
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Howdy all!

I’ve been reading up on the suggestions from last week as much as I can, and I think I have clearer idea of what I want to accomplish for this experiment. If anyone is interested, Dr. Bruce Land at Cornell has fairly watchable youtube lectures explaining some of the concepts (phase accumulator, interrupts, SPI, etc) which I found helpful, even though he’s using the PIC32 and a C compiler.

That said, the more I dig into this project the more my head seems to spin. I’ll write out what I’m thinking, and hopefully someone can help direct me to some resources to clear it up.

For the first attempt, I’m actually going to limit myself to one voice, without an envelope. If I get that down, I can work on some of the more advanced features I was planning on implementing. Hardware-wise, I’m more or less going to copy Garth’s 5-chip circuit potpourri computer with an added DAC0808 on one of the VIA’s ports. I’m still unsure about amplification — Garth’s DAC circuit mentions a variety of op-amps, but they also require some tinkering with voltage through a VIA.

I’m still more hazy on the operation of VIAs than I’d like to be, but it seems like I can use the 65c22’s T1 timer to set a pretty arbitrary IRQ timing as a division of Φ2. From there I think I’d like to rely on the CPU as a 16-bit phase accumulator, using the high byte as folks here have mentioned. I’m unclear as to whether it’s faster to do the 16-bit add by storing high and low bytes in RAM or by pushing the values onto the stack when I need to free up a register. This is actually pretty similar to Garth’s waveform generation interrupt example, which I hadn’t noticed until I started digging around.

I’m still far off from being able to build the computer, but I feel like I at least understand how this design would work from a high-level vantage point. Hopefully I can start ordering parts, doing NOP tests, and other things soon in preparation. We'll see I suppose!


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PostPosted: Sun Jun 03, 2018 4:46 pm 
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Sounds good to me!

There are a number of choices when programming the 6502 which seem like free choices but actually have their own pros and cons. One of those is how to use A, X, and Y for appropriate purposes, as they have different capabilities. Another is how and when to use the stack. You should of course go ahead and do whatever works for you - don't overthink it - but in time you'll find yourself getting better. I mention this because my guess is that using zero page locations is going to work better for you than using the stack when you're proceeding with your 16 bit arithmetic. It's reasonable to consider zero page as a collection of byte-sized registers, or indeed as a collection of byte-pairs: as and when you find yourself working with 16 bit pointers, you'll pretty much have to put them in zero page to use them, because the indirect addressing modes only work on zero page. (With one exception, which doesn't apply here...)

Do keep posting progress, and questions, and links to useful resources!


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PostPosted: Sun Jun 03, 2018 9:15 pm 
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cynlic wrote:
If I get that down, I can work on some of the more advanced features I was planning on implementing. Hardware-wise, I’m more or less going to copy Garth’s 5-chip circuit potpourri computer with an added DAC0808 on one of the VIA’s ports. I’m still unsure about amplification — Garth’s DAC circuit mentions a variety of op-amps, but they also require some tinkering with voltage through a VIA.

The DAC0808 is a current-output device, so an op amp is used to turn it into voltage.  The op amp doesn't care what the VIA is doing though.  My workbench computer does have a speaker amplifier whose input can come from the DAC op amp output or the A/D input, so you can monitor one or the other.

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I’m still more hazy on the operation of VIAs than I’d like to be, but it seems like I can use the 65c22’s T1 timer to set a pretty arbitrary IRQ timing as a division of Φ2.

Right; and the divisor can be any number, not just powers of 2 or whatever.

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From there I think I’d like to rely on the CPU as a 16-bit phase accumulator, using the high byte as folks here have mentioned. I’m unclear as to whether it’s faster to do the 16-bit add by storing high and low bytes in RAM or by pushing the values onto the stack when I need to free up a register.

Like Ed said, think of zero page as 256 bytes of processor registers, for register variables, indirect addressing, indirect indexed, indexed indirect, and more.  Besides producing faster and more-compact code, it offers addressing modes you don't get with the rest of memory (although the resulting effective addresses can point anywhere in memory).  The 65816 has stack-relative addressing modes; but the '02 is much more limited for doing stuff on the stack.  It can do it, but it's less efficient.  See my treatise on 6502 stacks (plural, not just the page-1 hardware stack), at http://wilsonminesco.com/stacks/ .  (Yes, you can have local variables and environments, recursion, and other goodies.)

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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PostPosted: Sat Jun 06, 2020 5:12 am 
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GARTHWILSON wrote:
The maximum S/N ratio you can get with a perfect 8-bit converter and no jitter is 50dB (from 8bits * 6.02dB + 1.76dB). (That's while there's signal. With no signal, the converter's output remains constant, with no noise at all if the reference voltage is quiet; so it's not like cassettes which gave tape hiss between songs.) [That's from the 6502 primer, in the circuit potpourri page's section on jitter. There's quite a lot of additional related information there too, so I won't repeat it all here.]

If volume reduction comes externally from a multiplying DAC or digital pot, the S/N ratio won't really suffer when you go below full volume.

The short video at https://youtu.be/UYAf_awh5XA is of a C64 playing recorded (not SID-synthesized) music at 48K 8-bit samples per second.  I'm sure you'll be pleasantly surprised at the sound quality.  I found out about it on Hackaday, at https://hackaday.com/2020/01/09/hifi-au ... -48khz-yo/ .

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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