Unfortunately, this is not always documented correctly, as some 65C02 documentation mistakenly assumes that DEC and INC have the same timing as ASL, LSR, ROL, and ROR; namely that INC abs,X and DEC abs,X take 6 cycles when a page boundary is not crossed, which is, once again, incorrect. DEC abs,X and INC abs,X always take 7 cycles.

I vaguely recall there are some anomalies in this area:

indexed addressing raises the possibility of a page crossing, which means an extra cycle may be required prior to the memory access. But for some indexed Read-Modify-Write instructions an NMOS chip will always include an extra cycle, even when no page crossing occurs. [...]

Table 7-1 of the WDC datasheet claims this issue has been corrected for the CMOS version, but in fact that's only true regarding ROL ROR ASL and LSR. INC and DEC are also Read-Modify-Write instructions, but the fix does not apply. Table 7-1 should read as shown below.

Yes. And the 'C02 fixed the problem... but, curiously, for some but not all of the RMW instructions. :!: Moreover, the documentation fails to accurately describe this! See dclxvi's thread, A 65C02 bug?

I wonder if the unimproved instructions [...] for compatibility purposes had to be left as-is?

If WDC wanted Apple to use the '816, WDC would have to redesign the chip. They did.

It was you, Ed, who suggested Apple's (possible) influence. Which is just a theory, but a plausible one, IMO. I can't think of a better explanation for why the 'C02 fix is so puzzlingly incomplete.

I'd be interested to know whether it can be confirmed that Apple's disk controller relies on the NMOS timing for INC and DEC with Absolute, X mode.