Note that the CS\ ("chip-select-not") on the RAM has the overbar over it, meaning it's negative logic.  (Unfortunately phpBB forum software doesn't provide any way to put it that way in a post.  WDC, in their early years, used software to make their data sheets which did not offer any way to do the overbar, so they added a "B" on the end of negative-logic signals, like NMIB for "non-maskable interrupt bar.")

...and pin 5 is a memory-lock output.

No one thought of simply using "/"?

Being inspired by C64 and living in the age of cheap (well, mostly) hardware, I've finally decided to build a simple SBC!

You'll need a reset circuit. It's not optional.

I don't think everyone is in agreement on that: it's a matter of opinion and judgement, and of course it's a function of how the SBC is supposed to be used. We've discussed this many times, and I'm surprised if you've forgotten.

The RAM will be active when this input is low, which is the opposite of how you have it.

You cannot join '138 outputs.  They'll fight each other.  In some cases, you can keep the '138 enabled all the time; but you'll want to make sure two things cannot be enabled at the same time, for example a VIA and a RAM trying to put data on the bus at the same time, as they'll fight each other.

Obviously you'll have to have some kind of I/O, or the computer won't be any good for anything at all.  Plan accordingly.

I would encourage posting your schematics in black and white.  We have a couple of forum members who are colorblind, and for one of them, the light-green lines may be just about invisible, and the green against yellow is problematic too.  In B&W, everyone can read it.

Before I go further, may I request you post your schematics in monochrome?

You didn’t mention whether you are going to use an NMOS 6502 or a 65C02. The latter is highly recommended for a number of reasons, not the least of which is the 65C02 doesn’t have the hardware errata of the 6502. Also, the 65C02 has strong output drive that swings rail-to-rail, whereas the 6502 has weak fanout that works at TTL levels. The output characteristic difference can give you grief.

Both versions of the SID are also TTL devices, so that is something else to consider. Of the two, the 8580 will be the much better choice. The 6581 needs a 12 volt supply, runs hot, is easily damaged by ESD and doesn’t follow the written specs for the device as well as the 8580. The 8580 can get by with a 9 volt supply, has less THD in its output and is less ESD-sensitive.

Garth answered this, but I’ll add a bit more to it.

Most SRAMs are designed to interface to Intel x86-style buses, which means they have three control inputs of interest (aside from the address and data pins): /CS (chip select), /OE (output enable) and /WE (write enable). /CS is controlled by your address bus decoding logic and is driven low (asserted) when the device is selected for access. When asserted, /CS, also referred to as /CE (chip enable), brings the SRAM out of hibernation and causes it to set up an internal data path to the cell that is to be accessed.

As the SRAM’s internal setup process is relatively slow, I always recommend /CS be asserted as soon as the MPU drives a valid address onto A0-A15. The 65C02 does this during Ø2 low, which means /CS should not be qualified by the clock (Ø2), since you will be unnecessarily giving up some timing margin.

Once /CS has been asserted, /OE would be asserted during a read cycle. The SRAM will drive the data bus one setup time after /OE goes low—that setup time is typically shorter than the /CS setup time. The MPU will sample the data bus near the end of the Ø2 high phase and latch the data at the fall of the clock. Although not essential in a 65C02 system, good practice will not assert /OE until Ø2 goes high, a hedge against data bus contention in some applications.

If a write cycle, /WE must be asserted, but only after the rise of Ø2. Qualifying /WE with the clock prevents data corruption due the buses momentarily being unstable shortly after the fall of Ø2. If writing is enabled while Ø2 is low, there’s the chance that two different cells in the SRAM might be “touched” as the address bus settles. Needless to say, debugging something of that nature would difficult.

Below is a circuit that fully qualifies reads and writes, and is suitable for use with hardware that has an Intel or Zilog interface, e.g., a typical SRAM or other non-65xx output device.

Wow, thank you for so many responses, I really appreciate this!
Can the outputs of 74x138 be joined via diode OR gate to mitigate this?

An AND gate is what you need. It's output will go low when any one or more inputs go low.

Oh, I think I finally got it. For some reason I kept thinking 74x138 outputs are X when inactive. Thanks for the pointer!

Not sure if I'm following: all 74x138 outputs & SRAM /CE & /OE are active-low, aren't they? (So the decoder will only ever select one RAM or ROM at a time)