I believe I know the answer to this but I want to make sure I'm not missing something.

I've seen some examples of wire wrapped computers where the person wired several IC's together via the VCC pin and then wire wrapped a decoupling capacitor to each VCC pin. This causes THREE wraps on the IC's in the middle.

Would it not be better to wire wrap IC 1 to the CAP and then the CAP to the IC 2? Then IC 2 would go to the CAP of IC 3? That would keep two wraps per pin max. I can show a diagram if needed.

The second way basically joins each IC via the CAP's instead of IC to IC with the cap spliced in. Hope that makes sense.

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Cat; the other white meat.

I think it's because wire wrapping is welding - three turns around a square post means 12 welds which are electrically parallel and therefore redundant. You can only wire-wrap around a square post, so you have to wrap the cap leads around a post, you can't wrap connecting wires around round leads.

Even if that weren't so, the connection of the VCC net needs to be reliable and low resistance, so you want as few links in the chain as you can, which is one reason you'll often see a star connection rather than a ring main.

One thing I didn't mention was the caps were connected via a square wire-wrap post.

My question is more on topology, I guess.

In other words, the examples I saw were like so:



The "I" represents the VCC pin of an IC. The "o" represents the positive connection of a capacitor. In the above example, the middle IC would have three wraps. One each for the surrounding IC's and one for the cap.

I was thinking the following would be better:



Each IC only has two wraps. Each capacitor only has two wraps. Is this electrically sound or would the first method be better?

Thanks

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Cat; the other white meat.

Ah, right. I think the second reason still holds: fewer series connections in the power net means better reliability and lower resistance.

There's another consideration, which is cost of rework. I think somewhere I read that it's best to wrap a-b, then c-d, and finally b-c, because then it's easier to unpick a mistake. If you wrap a-b, b-c and c-d then you need to dig deeper. But I'm not sure if that consideration applies here.

If you're thinking of doing things differently, and it's a hobby thing, I'd say go ahead. You're not going to make hundreds of them and they won't be running for thousands of hours.

That is, assuming I haven't missed a vital reason - so we'll see what others think.

I read the same thing too.

About a-b, c-d and then b-c. So I was wondering if that also applies to the decoupling caps.

Thanks!

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Cat; the other white meat.

For best AC performance (ie, regarding the way the circuit reacts to the fast rising and falling edges, not particularly the clock rate), put the capacitor on the WW side of the board and solder its leads directly to the IC socket's WW pins first, way down at the base, as close to the body of the socket as you can. (Just be careful not to let solder get any higher on the pin where you will need to do the wire wraps later.)

The reason is that pin length, wire length, capacitor lead length, etc. all have inductance which we're trying to get rid of. If you want to go to a greater extent, you can solder a bypass capacitor to the top of the IC, to the top of its own power and ground pins, with its leads as short as possible, so you can get it closer to the die (ie, the silicon chip itself inside the IC) and eliminate the connection length presented by the socket itself. (Just make sure your solder job doesn't prevent the IC pins from going into the socket!)

In 1983, when I started working at the VHF/UHF power-transistor manufacturer, I knew the theory, but it took experience for the reality to hit home. (In fact I've continued to learn more about it in recent years as I've worked in digital.) Back then, I measured the inductance of a leaded disc (or was it monolithic ceramic) bypass capacitor, and found that it turned inductive above only 10 or 15MHz, because I had a half inch of lead length on each side! If you want to run a computer at, say, 5MHz and 74HC parts (whose output rise and fall time is typically a slowish 7ns), a bypass capacitor would preferably not be be turning inductive below about 50MHz which is five times as high as what I measured above. In reality, it won't be that good without a PCB, but you can still get some pretty good performance with WW if you really do a good job.

Next, you want to minimize the inductance of the power and ground connections from each IC to its neighbors, by making those wires as short and direct as possible, without curves and corners or detours to capacitors like your second ASCII diagram shows.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I agree 100% to Garth.
Bypassing with long leads soon becomes useless due to the lead inductance. HC technology has brutal fast edges. Taming them isn't easy. If you don't need the speed, driving capabilities or power savings, using 74LS might be a choice - LS is much slower and much easier to handle.

GaBuZoMeu, you might be thinking of 74AC. 74HC and 74LS are approximately equal in speed, but HC has other advantages over LS. AC is approximately three times as fast as HC and LS.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Correct. Propagation delay isn't much different, but what's about the rise and fall times? I have no DB at hands...
What I remember when our company switches to HC(T) was some ugly pseudo-randomly appearing bugs. It turns out that they weren't random but depends on how many adress/data lines per driver do switch. Improper decoupling was the reason. Adding short leaded caps helps alot.
Thinking of todays EMI requirements using these old style circuits makes me shudder

It helps that we now have much better packages with short internal connections.

74AC switching speeds approach sub-nanosecond levels, which is substantially faster than 74HC. Also, 74AC devices drive much harder.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Every time I look into this kind of thing, I'm reminded of how much information there is and that wading through it all is not a quick thing.

My book on 74LS is not very complete; but on 74HC, it looks like it couldn't be much slower and still meet the propagation delays (PD's) for the simplest ones, according to my National Semiconductor books. On the 74HC00 for example, it says typical PD is 8ns while typical rise and fall time is 7ns, both at 6V. It's 9 and 8ns @ 4.5V. The PD is measured to the half way point of the output swing, not 90%, but it does also include half the input swing which is about the same rate in the testing. Don't ask me why they don't specify it at 5V.

I spot-checked a few 74AC's to compare, and the PD's were anywhere from about twice as fast as the equivalent 74HC to nearly five times as fast! There seemed to be the least difference in the simple ones like 74xx00, while the more complex ones like 74xx5xx showed greater differences. For the 74AC, the 18-page "descriptions and family characteristics" article in the front of the book shows the rise and fall times bottoming out at around 1ns, give or take, depending on lot, temperature, etc., which is seven times as fast as the 74HC numbers given above. And as BDD said, the drive strength of 74AC is much greater than 74HC.

Regarding 74HC versus 74LS, the HC has slightly shorter (ie, faster) PD's than 74LS for most parts, with just a few exceptions.

In virtually all cases, I would recommend 74HC above 74LS. The only strength LS has over HC that I can think of is that it's less vulnerable to damage from static discharge; but with reasonable handling, I seem to have never damaged an HC (or any other CMOS part) with static.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I was astonished: I fetched a Motorola DB and didn't found a tr or tf specification. I took National - same. Then TI - ah, I had luck - tt was specified, but the same value(s) for all devices and such a broad range (minimum to maximum roughly a factor of 10) that it wasn't really helpful. I took Philips (NXP) - luck again, but the numbers were twice or more as high as TI's ? Fairchild ? Nothing...

Then I tried my luck using the WEB - I found this http://ve2zaz.net/referenc/LogicT.htm

At least the numbers look reasonable, although I "remember" the differences between LS and HC "bigger".
But yes - you're right, today there is no reason to use LS unless one wishes to have a bigger quiescence current

I always solder the capacitor onto the bottom of the wire wrap
post. It is just a single hook and just enough solder to make the connection.
The rest of the wire wrap post is still available to wrap the wires.
I usually use wire wrap boards with plains for VCC and Ground. I don't
usually depend on wrapping to connect VCC and Ground. If you are using
two wrap post, it is impossible to do a proper VCC and Ground grid with
two wrap post as that takes 3 wraps, on a 3 wrap post.
I only use wraps on these for local use, such as grounding unused
inputs.
Dwight