Ok, I'm looking at the example in Garth's primer for a memory map with 1 32k SRAM (16k available), 32k ROM, and room for much I/0.

I have been studying the varies combinations possible, and found one scenario that confuses me.

Imagine A15 is LOW, and A14 is HIGH. As I read it, this is to select I/0 addresses. Ok, makes sense.

So if that combo is there, and the phase2 clock is HIGH, you would have I/O plus SRAM's CE pins selected. The OE of SRAM would still be deselected, but you could still write (correct?)

Ok, that is fine since that memory is not actually reachable in this scheme, and write garbage there doesn't matter.

what confuses me is there is still a line from A14 to the SRAM. What is it for? Is it just a bad idea to have that pin not connected?

Think one step further

If A14 wouldn´t be connected to the RAM, what do you do with the corresponding pin?
a) tie it lo => any access to $4000..$7FFF would look exactly like an access to $0000..$3FFF. => You need to gate /WE as well as /OE to prevent writing to $0000..$3FFF.

b) tie it hi => same story, just different memory section.

=> using A14 saves additional logic.

OK?

Yeah, actually I worked that out as I typed my message.

I still posted it to make sure. You confirmed it for me!

Many thanks!

Another way to do it would have been to replace the left-most NAND with a NOR, and connect its inputs to the processor's A15 and A14, then tie the SRAM's A14 either high or low. That way, the processor's A14 would be involved in the SRAM's CS\. That would require an additional IC though (a 74xx02), which I was trying to avoid. On the plus side, the '02 might have saved a small (actually pretty negligible) amount of power, since the SRAM would not be selected when you're writing to I/O. (You can't have the RAM and I/O swap places, because you have to have page 0 and page 1 in RAM, since they have special functions.)

As it stands, the use of A14 keeps you from corrupting the used part of the RAM when you write to I/O and the RAM is selected because A15 is low. With A14 tied to OE\, you can never read the upper half of RAM, since that's where your I/O is. You want to be able to read the I/O without bus contention.

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