Hi all.
Im thinking of building a 6502 system comprising of.....

W65c02-10mhz
Rockwell6522 . 2off
6850 1 or 2 off (1 for midi)
Sid (prob swinsid as got 2) 2 off
V9958 video......Yea can see this being a pig......

The problem is speed. The sid afaik tops out at 1mhz so im looking for a wait state circuit. I saw a circuit on here using and gate and 74 flippyflop and i simulated it ok but i really need 2 wait states but i dont want to go through the gal route. Want to use standard logic.

Im planning to use a 7.2738 xtal divided by 2 for cpu speed at 3.6mhz. 1 wait state for 1.8432mhz for I/O and 2 wait states for 0.9 mhz for SID.

Does anyone have a circuit i could use ??

Many thanks . Lee

Welcome! Here are circuits for one wait-state and for two. If you're the cautious type you may wish to avoid connecting the FF output directly to the RDY input of a WDC CPU. Instead, make the connection using a resistor with a capacitor in parallel to it. But some people consider a direct connection (no RC) to be satisfactory. See here for more discussion.

To use these circuits your decoding circuit must be one which causes the chip-select to go low prior to the rise of PHI2. Not shown: the /SET and /CLR inputs of the FF are unused, and must be tied high.

For initial debugging it's maybe best to have no wait-states at all (tie RDY high), and simply use a crystal that's sufficiently slow. *After* you've gotten that working you can can add the wait states and the faster crystal.

Have fun!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Hi Braincell1973!
One 74109 appears pretty good, if the device needing wait states is the only one. But it seems, there is the need for two generators with collecting logic on inputs and outputs, i.e. 3 or 4 IC's finally.
May be you should not be so resolutely refusing GAL's?

Vladimir

Thanks, Jeff, Vladimir.

Maybe i should start at 0.9mhz to ensure things start well.

Looks like i need to investigate how to ensure CS goes low before PHI2.

As a beginner and from what i have read it seems that the SID is 1mhz max, a la C64.
V9958 is 2mhz max
My 6522's are from ebay so assuming again 1mhz when they arrive.
My 68B50's are B grade so 2mhz, chose multiple of 1.8432mhz for baud after reading Grant Searle's "Simple 7 chip 6502" which is how i got into thinking i should make 1 of these

eventually will need to apply wait state to address ranges.

The reason for trying to run before walking is im thinking of making cards from dirtypcb (I know the 6502 primer suggests not running busses off board) so this system can be extendable. but also hoping 3.6mhz is slow enough to cope with that too

Im not especially against GALs but only have a 866 programmer from ebay and heard lots of problems from people trying to program them, Plus my electronics skills are also still learning

Lee

Hello again

Here's an update to the diagram, showing how multiple devices can be connected. The AND gate collects the inputs, which I think is what Vladimir was talking about.One thing this circuit doesn't offer is various numbers of wait-states. Each I/O device that's connected will get 2 wait-states, and of course any I/O devices not connected will get none. That's not such a bad solution. Maybe 2 wait-states is more than the 68B50's require, but only a small performance loss will result. What's probably more important is having a simple circuit that's easy to understand and build.

BTW, at some time in future you may wish to install 65C22's from WDC, which are rated to be as fast as the CPU and will require no wait-states at all.

I didn't mean to make it sound complicated. It's actually easier to make a decoder that meets this requirement than to make one that doesn't.

But I'm sorry to say some of your devices will require something more complex than just wait-states. I'm sorry this didn't occur to me sooner.

Using the 6522 as an example, that chip uses the PHI2 signal internally as a timebase -- to operate the timers, for instance. Although wait-states will stretch the bus accesses from the CPU, thus making them longer, that doesn't change the fact that at all times PHI2 is running faster than specified. The timers and any other internal functions using PHI2 may fail to work. This issue will affect most or all of the I/O chips on your list. (Sorry -- I'm not familiar with all of them.) It's possible you might get away with the violation of spec's, but of course that's not guaranteed.

The problem can be overcome -- the extra logic isn't horribly complex. IIRC some of the BBC computers from Acorn manage it.

I need to cut this short. Bye for now,

Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I believe, this is a right way. There will be less problems and more likely that everything will work right away.

Don't worry. This problem exists either for high clock frequencies (may be >8-10 MHz or so) or, as Jeff mentioned, for the case of extremely bad address decoder. Your CS, I believe, will always have enough time to be ahead of rising edge of Ф2.

I do not insist on GALs. It is entirely up to you. Is it interesting to you or not, this is most important thing. If not, do not get distracted from the matter, GAL's would be overkill. The Jeff's recent suggestion with 2 w.s. for all I/O's is a good trade-off between complexity and performance.
BTW, wait states is a thing not to focus initially. Most of the work can be done at a low clock frequency, w/o wait states.
Concerning memory map, you might think of right now.

Thank you, Jeff. As for me, this is very interesting information, something to think about.

Vladimir

I would like to offer a few suggestions. These are only suggestions.

1) Perhaps running at 1 MHz instead of 3.6 MHz.

In my personal experiences, the only time I ever needed more speed from a Commodore 64 was doing software scrolling. And even at 1 MHz, I was able to pull it off. So a lot can be done with 1 MHz. Plus, the circuit gets much simpler.


2) Instead of using a real SID (or SWIN SID), you may want to use a Propeller micro-controller from Parallax. A *very* accurate SID emulator was written for it and you can technically get 4-6 SID's running at the same time. The advantage is that the Propeller might be fast enough to interface directly at nearly 3.6 MHz if you must run at this speed.


The Propeller is also *VERY* easy to get into. You need almost nothing to get it up and going...


Now, I certainly don't want to discourage anything...I was just thinking the above suggestions might be easier.

_________________
Cat; the other white meat.

Thanks for the great replies.

I have been giving this lots of thought over the last few days before posting on here.

Excellent point about the clock stretching Jeff as that hadnt occurred to me, So now im wondering if the IO chips need the main clock or can i supply a secondary clock to them ???

So, If i had a7.2mhz crystal and used a ripple counter (hef4040b? good to 20mhz @5v) i could generate the other freqs at the same time as the main clock, i could also set up a jumper to set system speed for testing and too bypass wait states.

I really want to get the most from making the PCB's as i dont want have to remake any (4 week delay :/ ) also i want the most ,bang for buck out of them for future.

As soon as i can get the CPU/RAM/ROM board made i can improvise rest on perf while im designing other boards,

As for Memory map.....

16 or 32k for ROM selectable on jumper
32 or 48k for RAM selectable on jumper
IO page 1 at FC00 thru an ac138 for 8 IO's - 0 or 2 WS (again jumpered)
IO page 2 at FD00 thru an ac138 for 8 IO's - 0 or 1 WS (again jumpered)

Should be plenty for just about anything.

Using a modular design is 3.6mhz even attainable ?? Guess if its on a jumper it should be easy to find out

For storage i am waiting for a ch376 to arrive, (8Bit bus, Fat decoding on board......Nice )

The V9958 may be a bit of a problem as i cant find all info yet but will make a separate video board, Idea is i can use serial through 6850 as a start until i can get video board made.

Going to slightly adjust the basic rom on Grant Searle's webpage to get me up and running while i learn 6502 assembler

Im hoping to get some schematics done over the next few days if possible.

The propellors sound interesting and will have a look into those.

EDIT: ....... WHAT A PILCHARD........ Can see chips use PHI2 and not the input Clock *FACEPALM*

I'm sure 3.6 MHz would be possible. In fact, there used to be 7 MHz (IIRC) accelerators made for the Apple IIe. And the Commodore 64 had a 20 MHz accelerator. Not sure how they were engineered, however.

_________________
Cat; the other white meat.

Hi guys!

I had some thinking of the problem described by Jeff. Supposing we have an I/O device that requires 1 w.s. and we want apply to the Ф2 input of the I/O chip the reduced clock frequency, say Ф2/2, i.e. MPU clock divided by two. The I/O chip is glad, the frequency is in permissible range, low freq. is not an obstacle for work. MPU has problems: not every MPU cycle is suitable to initiate the I/O data transfer. The data transfer with 1 w.s. require two MPU cycles. A successful case is when between the MPU cycles occurs rising edge on the Ф2 input of I/O/ chip. Unlucky cycle must be wasted (may be, the W.S.Generator must insert one extra w.s.). Than all occurs as usually, there is regular data transfer with 1 w.s. Right? In such a system, W.S.G. must track odd and even MPU cycles to skip unlucky ones.

Vladimir

Edit: attached diagram and an amendment:
I wrote above: "may be, the W.S.Generator must insert one extra w.s."
I made a mistake. It can not just be extra w.s. May be Ф2 on MPU must be stopped for one cycle, since MPU must not assert the address and must do nothing during wasted cycle.

Drawing a timing diagram might help. It would look something like the attached.

The RDY line has to be driven low as soon as the chip select detects a slow I/O area. Then it has to be driven high again on the CPU cycle just before the end of the slower I/O clock. Finding the CPU cycle just before the I/O cycle ends can be done with a shift register that begin shifting on the first edge of the I/O clock.
One thing to note is that it’s desirable to drive the slow I/O clock from the negative edge of the CPU clock so that the falling edges of the I/O clock and CPU clock are synchronized.
An low going edge detector could reset a shift register which shifts out RDY for the I/O. The third tap of the shift register would be used. (The input of the shift register is tied high).
A 74AC164? plus a FF and a low going edge pulse generator (RC network) should just about do it.

_________________
http://www.finitron.ca

Hmm... using a 0.9MHz clock for I\O and SID generated by a Johnson counter (74164 shift register plus one inverter)
probably would simplify the wait state generator.

It's just a thought.

;---

Edit:
There is an article about RDY generation from fachat which might be useful.

Hi All,
Knocked up the memory map decoding schematic, What do you all think ?

Using the 521 not the 520 in the schematic......



The jumper is obviously to select 16 or 32k ROM ...



Welcome your comments

Lee

Please post your schematics in monochrome for easier reading by us old dinosaurs.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Apologies...... Mono





lee