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 Post subject: Layout question
PostPosted: Thu Oct 27, 2016 2:00 am 
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Joined: Sat Jun 04, 2016 10:22 pm
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Location: Australia
I'm building a computer, based on a 6502, and I tried building a relatively stripped-down version of its current form on a solderless breadboard, but I ran into problems, with some of the connections being intermittent or just plain dodgy. So I decided that I'd get a bunch of IC sockets and solder the thing together on a soldered breadboard. I know that this is almost as bad as the plug-in breadboard, or at least that somebody will raise the point, but I'm just prototyping the thing at the moment; getting it working before I turn it into a battery-powered portable device using SMDs and/or PLCCs.

I've laid out the board, but I haven't soldered anything down yet. Can you see any ways this layout can be improved?


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 Post subject: Re: Layout question
PostPosted: Thu Oct 27, 2016 5:51 am 
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Hi,

I am no expert, because I am working on my first computer on my own. I think that you should put them vertically and put EEPROM and RAM adjacent to each other. You can save lot of space and wire it nicely. They have almost same pin out. Also always try to make all the ICs close together. Anyway, how did you get/made the stickers? I want them too!


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 Post subject: Re: Layout question
PostPosted: Thu Oct 27, 2016 6:05 am 
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( I see pogof has posted as I was preparing my own post. I agree with the suggestions mentioned. )

I like to keep the lines of the data bus more or less parallel with one another so they don't cross over one another much. This helps avoid a "rats nest" tangle. Same for the address bus.

One nice thing about the address bus is that only a few of the least-significant lines (eg: A0, A1, A2, A3) extend to all the main chips. The remaining address lines -- the majority -- don't. They connect only to CPU, memory and possibly the decode logic. For this reason it makes sense to keep the CPU and memory chip(s) close together. Wires that don't have far to go make for a tidier board.

The attached images show one possible layout which keeps the memory and CPU close, and also has minimal crossing-over of the address lines and minimal crossing-over of the data lines. Blue is for the data bus, and red is for the address bus. Obviously I haven't drawn all the lines -- in particular, A15-A8 are missing entirely. Mainly I just wanted to illustrate how you can take advantage of the pinouts of the various chips, and get a wiring layout that's fairly orderly.

I hope some of these ideas are helpful. I realize the board you've chosen may have etched pads that lead you in a different direction. But if it's "pad per hole" then you have freedom to orient things any way you please.

Have fun!

Jeff

ps- oops, I omitted the RAM! But, as pogof said, it has almost the same pinout as the ROM, and should go beside it.
Attachment:
layout.png
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Attachment:
buses.png
buses.png [ 722.64 KiB | Viewed 1757 times ]

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 Post subject: Re: Layout question
PostPosted: Thu Oct 27, 2016 7:55 am 
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Thanks for the suggestions. I shall implement them.

I got the labels from this Github repo: Link. They're in the ChipLabel directory. I just printed them out and stuck them on with Blue-Tack. I don't remember which file I ended up using, and I seem to remember that the PDF version is no good.


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 Post subject: Re: Layout question
PostPosted: Thu Oct 27, 2016 8:35 am 
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When soldering a computer on bread board with wires,
a nice approach is first to do GND and VCC with bare wire,
then to use wires for the address\data bus with colors according to the resistor color code
like D0=black, D1=brown, D2=red, D3=yellow (if you don't have orange wires), D4=black again...
then to use blue or green wires for the control lines.

This might save you some trouble when debugging your contraption.

Jeff nicely arranged the chips. :)

BTW: 68020 with 32 Bit data bus:
Image

Good luck, and happy soldering...


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 Post subject: Re: Layout question
PostPosted: Thu Oct 27, 2016 8:47 am 
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No possibility of cross talk when your wiring is random!


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 Post subject: Re: Layout question
PostPosted: Thu Oct 27, 2016 9:06 am 
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Here's my slightly extended version of Grant Searle's 6502 board http://searle.hostei.com/grant/6502/Simple6502.html The original 6 chip design has been extended with an expansion header and a '138 to break the normally unused 8k into 1k chunks, one of which has the extra ram chip for "local" memory for any expansions.

The colour coding for the wiring is red/black for power, blue for the address bus, yellow for data bus, white and green are the remaining logic , chip selects, clock etc.

The vertical arrangement does greatly simplify the wiring, I don't know clear it is from the photo, but the 6502 is upside down relative to the other chips.

De-coupling is done with 0805 surface mount capacitors on the wiring side of the board. This board is clocked at 1.8mhz, as per Grant's design, but I've had other designs, made the same way run comfortably at the WDC 65C02's rated 14mhz.


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File comment: And the wiring side
wiring.jpg
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File comment: Vertical arrangement Component side
Component.jpg
Component.jpg [ 78.4 KiB | Viewed 1735 times ]
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 Post subject: Re: Layout question
PostPosted: Fri Oct 28, 2016 9:58 am 
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Thanks for all the advice; I'll very probably use most(if not all) of it.
I'll also try keeping the wires fairly flat to the board. I think it'll be neater that way. I plan to do so by starting at one end and moving across.

Also, while I remember: I altered some of the labels shown. I have two identical ROM chips, and the red dot on the one shown mirrors a blue dot on the other one. I put the actual part number on the label as well. It's not really visible in the pics, but I also marked the 'C02 label with red and blue dots to show whether the pins were inputs, outputs, or both. Felt-tip pens can be so useful sometimes.


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 Post subject: Re: Layout question
PostPosted: Wed Nov 02, 2016 5:38 pm 
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FYI, if I could spam this thread for a moment...I am 99% done with a backplane layout for a 6502 board. I just need to finish the silk screen text and send it to the PCB house.

I created it for this exact same reason. I want to prototype 6502 computers and I got tired of the rats nest of wires everywhere and always trying to figure out a clean way to arrange things.

Anyway, sorry to hijack this thread. I will post a separate thread when I get my first batch from the PCB house.

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 Post subject: Re: Layout question
PostPosted: Wed Nov 02, 2016 11:20 pm 
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I don't think anyone mentioned the following yet; if they did, I apologize for wasting time.

It's perfectly okay to swap address bus lines with each other, or swap data bus lines with each other, to simplify the routing on (static) RAM chips. The RAM chip itself doesn't care how the data is stored, and as long as you retrieve the data from the same place as where you stored it, the rest of the system doesn't care either. For example, here's how I connected the 128K RAM chip in my project (I could have gone further but I wanted A15 and A16 non-swapped so that it would be possible to use a 32K or 64K chip instead of the 128K chip, and not lose one of the address lines in the middle of the bus):

Attachment:
Screenshot 2016-11-02 19.12.50.png
Screenshot 2016-11-02 19.12.50.png [ 77.04 KiB | Viewed 1635 times ]


As you can see, the swapped address and data bus lines result in a nice routing without jumpers (click to enlarge).

Attachment:
Screenshot 2016-11-02 19.18.12.png
Screenshot 2016-11-02 19.18.12.png [ 107.48 KiB | Viewed 1635 times ]


You can swap address and data bus pins on EPROM or EEPROM chips too but when you do that, you'll have to somehow swap the appropriate bits when you program the chip. I haven't used an EPROM burner in years but I imagine current software should make it easy to deal with swapped pins on the address and data buses.

(For more info about my project, see https://hackaday.io/project/3620)

===Jac


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