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PostPosted: Fri Apr 29, 2016 7:26 pm 
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Joined: Wed Apr 02, 2003 9:18 pm
Posts: 33
I'm having some serial issues, and I'm not quite sure where to go with it.

I've attached two pictures -- one expected output, and one actual output. I've tried changing baud rates and from a WDC 65c51 to a Rockwell 65C51, and both exhibit the same behavior. I don't have another MAX233 to try, but one is on order.

What is really strange is that after the initial patterns, I can type and hold down keys on the keyboard and I get no errors whatsoever. Its almost like it needs a few seconds to get ready...

Pressing the reset button produces the same output. If there were serial errors, I would have expected different output each time.

Has anyone seen something like this before?

EDIT: Forgot to add my code:

Code:
;;
;; Read input from the keyboard, and echo to console.
;;
.PC02

iobase   = $C000
iostatus = iobase + 1
iocmd    = iobase + 2
ioctrl   = iobase + 3

.segment "CODE"
.org $E000

start:      sei      ; no interrupts
      lda #$00
      sta iostatus
      lda #$0b
      sta iocmd   ; Set command status
      lda #$1e
      sta ioctrl   ; 9600,8,N,1

;; print ascii codes
test:
      ldx #$05
loop:      lda #$20
l1:      jsr write
      clc
      adc #1
      bpl l1
      lda #$0d
      jsr write
      dex
      bne loop
      

;; Load a character from the keyboard and store it into
;; the accumulator

getkey:    lda iostatus   ; Read the ACIA status
           and #$08       ; Is the rx register empty?
           beq getkey     ; Yes, wait for it to fill
           lda iobase     ; Otherwise, read into accumulator
      jsr write
      jmp getkey

;; Write the current char in the accumulator to the console

write:     
           ;sta iobase     ; write to output.
      ;jsr delay_6551
      pha
write1:      lda iostatus
      and #$10
      beq write1
      pla
      sta iobase
      ;cmp #$0d
      ;bne done
      ;lda #$0a
      ;sta iobase
      ;jsr delay_6551
;done:
      rts

delay_6551:   pha
      txa
      pha
      tya
      pha
      ldy #2      ; Clock speed in MHz
minidly:   ldx #61      ; lessened from 68 for 1.8MHz
delay_1:   dex
      bne delay_1
      dey
      bne minidly
      pla
      tay
      pla
      tax
      pla
      rts
      
; system vectors

.segment "VECTORS"
.org    $FFFA

.word   start       ; NMI vector
.word   start       ; RESET vector
.word   start       ; IRQ vector



Attachments:
File comment: The somewhat garbled output
IMG_20160429_140826.jpg
IMG_20160429_140826.jpg [ 4.73 MiB | Viewed 949 times ]
File comment: The expected output
IMG_20160429_140847.jpg
IMG_20160429_140847.jpg [ 3.17 MiB | Viewed 949 times ]
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PostPosted: Fri Apr 29, 2016 7:34 pm 
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Joined: Thu Dec 11, 2008 1:28 pm
Posts: 10986
Location: England
Oddly enough it looks more like a parallel issue - it looks like bit 1 is unreliable. The sequence
012345678
is mutating to
030347678
and that's always a flip of bit 1. Similarly for the alphabets.

Is the databus side of the socket for your serial chip well-connected?

(What kind of computer are you running? What kind of construction technique?)


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PostPosted: Fri Apr 29, 2016 7:42 pm 
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Joined: Wed Apr 02, 2003 9:18 pm
Posts: 33
Ed,

Its all on a breadboard...and all run through a single 1.8MHz oscillator. It sounds like you are saying that D0 might be bad?


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PostPosted: Fri Apr 29, 2016 7:44 pm 
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It's almost like D1 (which is bad) is getting the value of D0.
Edit: but not exactly that. Some of the sequences are coming out slightly different from each other.


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PostPosted: Fri Apr 29, 2016 8:27 pm 
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Ed, you're a genius! I replaced D0 and D1 and it works a charm :) Thanks!


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PostPosted: Fri Apr 29, 2016 8:28 pm 
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That's great!


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PostPosted: Fri Apr 29, 2016 8:50 pm 
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Note that you can simplify your code too, since you're using the CMOS processor.

  • LDA #0, STA can be replaced with STZ.
  • TXA, PHA can be replaced with PHX.
  • TYA, PHA can be replaced with PHY.
  • PLA, TAX can be replaced with PLX.
  • PLA, TAY can be replaced with PLY.
  • CLC, ADC #1 can be replaced with INC A (alias mnemonic being INA).
  • SEI can be eliminated from the beginning of any reset or interrupt-service routine, since setting the interrupt-disable bit is already an implied, automatic part of the sequences. (This is true of NMOS too.)

_________________
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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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PostPosted: Sat Apr 30, 2016 4:56 pm 
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Joined: Wed Apr 02, 2003 9:18 pm
Posts: 33
Hi Garth,

Thanks for your thoughts...I hadn't really gotten to optimizations yet for two reasons: I've built a target with SyMon, which only supports NMOS 6502 instructions; and I haven't really looked at the 65c02 instructions yet, as I come from assembly with my trusty C64 and C128. I just wanted something to prove that the thing worked...the quality will come soon. :)

I built a new target in cc65 for my board...I love how easy Uz made it to target a new board! Many kudos to him and to Oliver for maintaining and extending it!


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