I'm working on several side projects but my main goal has always been to design my own SBC. As I work on these side projects, I learn new things...

So, I think I finally have a more sane decoding scheme that isn't crazy or hard to build. I would love everyone's input.

I'm not at my normal computer at the moment so I can't upload a true schematic but I have attached a hand-drawn version.

The basic plan is 32K RAM, 16K ROM and 6 I/O devices. I don't think I really need that many. So I could shorten the list.

Here is the memory map:



I like the idea of full page I/O because I plan on using a micro-controller as one of them and I need the 256 bytes for it.

Here is my *CRUDE* schematic:



So I'm thinking I would need 3 quad-input NAND gates for the decoding logic. One would be for RAM, ROM and one I/O. And another would be for four I/O. I could ditch the third one and "settle" for 5 I/O devices.

What do you guys think?

I haven't spec'd the part yet. But I have a few 74HC132's around. Top speed for the computer would be 1-2MHz.

Do you think the setup would work with an even faster clock? Say 4-8 MHz? I imagine I would have to use faster NAND gates.

Thanks!

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Cat; the other white meat.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Would there be any advantage using ɸ2 qualified /RD and /WR signals instead of a ɸ2 qualified RAM select signal? You would use the A15 address line for the active-low RAM select ($0000..$7FFF). Also, if you think you might use an EEPROM and you'd like the capability to program it in-circuit, I think EEPROMs require mutually exclusive /RD and /WR signals, don't they? Please correct me if I'm wrong, guys.

I wouldn't mind trying this simple decoder scheme using the CLC (configurable logic cell) modules on a little 14-pin or 20-pin PIC.

AH yeah! That's much better. lol

I don't know what I was thinking. Anyway, I certainly can't take credit as I got the idea from the primer site.

So I should be able to use only one NAND chip right? Even for all 6 I/O's? Plus I think I can invert A14 using VCC and one of the NAND inputs.

I'll draw up another schematic soon.

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Cat; the other white meat.

I would also recommend the idea of Micheal to have a master read and write signal that is connected to the OE and WE signal of ROM / RAM. These signals are also useful for non 65xx peripherals like the UARTs often proposed by BDD. This takes 3 NAND gates. As Micheal said the best is to use A15 as the chip select for the RAM. THen you use the forth NAND gate with its inputs cnnected to A14 and A15 for the chip select of the ROM. Then I would propose to add a 74ACT138 as the IO address decoder. A15 would be connected to active high enable and A14 would be conncted to one of the active low enable inputs. The second active low enable input is connected to GND. Then you connect A13, A12 and A11 to the inputs A,B and C of the 74ACT138. With this you get 8 IO ranges. So with only two descrete TTL logic chip you have a complete address decoder. Note that 65xx peripherals can share one of the IO select lines using the activ hgh chip select to distinguish the individual chip using some of the unused addresss lines, in this case A10 to A4.

I'm not familiar with CLC in PIC's. Is that some type of low-level CPLD/FGPA functionality? That would be pretty awesome if it were.





So the basic principal is that using the 1 of 8 decoder, I get 8 different IO devices using A[13:11]. But I'm not sure I understand what you mean about the 65XX sharing IO lines. I'm thinking 8 IO devices is plenty (up from my original 6). Or, do you mean something else?




That chip looks pretty awesome (10.9ns propagation delay) but it doesn't appear to run at 3v3. I guess for that kind of speed you need 5v. Hmm. I could run everything 5v except my mcu. I planned on having 5v available anyway.




Which is exactly why I wanted to consult the experts. Not only did I learn something, now my chip count is reduced by two.

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Cat; the other white meat.

In regards to using the 74ACT138 as a general purpose decoder, there is no good reason to use 74ACT logic unless it is being driven by 74LS logic, or by devices that generate TTL-compatible outputs. Almost all 74ACT devices are slower than their 74AC equivalents, and are theoretically more noise-sensitive. This also applies to 74HC vs. 74HCT logic. While the speed of any one device may not be critical, the prop delays through a series of devices can quickly add up. So this should be a consideration in your design.

In general, if all devices (MPU, I/O hardware, RAM, etc.) in your system are CMOS then all logic should be CMOS, which means no 74ACT or 74HCT should be used at all. I generally recommend 74AC if the Ø2 clock will exceed 8 MHz.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Here is the circuit I devised for POC V1.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

BDD is right, use the 74AC138. First it is more compatible with the output levels of the W65C02 (although this is no issue in this case) but more important the AC devices are specified for a voltage range of 2.0 to 6.0 volts. Of course running your system at 3v3 limits its max speed to approx 8MHz.

A couple single chip solutions come to mind;

Thanks for the suggestions!

I didn't know that about AC vs. ACT.

I added some 74AC138 & 74AC139's to my Mouser shopping cart. I think all I have at home are LS versions.

Concerning 3v3 and maximum speed, my target speed for my first computer is going to be in the 1-2MHz range with 4MHz being "high speed".

SBC#2 or 3 will probably be an '816 running in the 8-10 MHz range. So I have some time.

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Cat; the other white meat.

Hi Micheal, I would rather not use the '139 to create the PHI2 qualified signals as the '139 is rather slow compared to a 74AC00 and due to the very short data hold time provided by the W65C02 and the required data hold time of normal speed RAM (55ns or slower) this could violate the guaranteed times for writes.

cbmeeks, if your goal for the clock range is in this range you could use the clock from the UART. 4MHz with this minimalistic decoder with short delays and without using buffers for the data bus is definitively going to work. My simple systems, using only one 10ns GAL for all the glue, run at 11MHz even when built on a breadboard. Of course at 5V and using a fast (20ns) RAM.

I'd really like to get into that. I've done a little FPGA but FPGA is extreme overkill for this (not to mention hard to design boards).

I mean, 2-3 small logic IC's isn't the end of the world. But a small, through-hole GAL would be nice. However, everyone seems to recommend small CPLD's for anything NOT FPGA. Heck, many people say CPLD's aren't worth it. Which I don't get.

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Cat; the other white meat.

CPLDs have the advantage of being able to consolidate many logic functions into a single device, with a guaranteed pin-to-pin propagation time that will simplify timing calculations. GALs offer guaranteed pin-to-pin prop times as well, but being SPLDs, are limited in total logic functions, inputs and outputs. Even a small CPLD (e.g., an Atmel ATF1504AS) has considerably more logic resources, as well as many more uncommitted I/O pins (32 on an ATF1504AS). In my opinion, a small CPLD makes more sense with what most of us are trying to achieve.

That said, you can build a pretty decent system using only discrete logic. My POC V1 unit uses only 74AC and 74ABT logic in DIP packages, has 52KB of available RAM, 8KB of ROM, a 2KB I/O block (RTC, DUART and SCSI), and runs at 12.5 MHz, which is the maximum speed at which the I/O is stable (there is no wait-stating). RAM, ROM and I/O select logic is such that no more than two gate delays are present in any given circuit. I am certain that if it weren't for the limitations of the I/O hardware I could run the unit at 20 MHz.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I'm going to order some AC series logic. But I'm assuming LS would be fine for 1-2 MHz systems?

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Cat; the other white meat.