BigDumbDinosaur wrote:
You might want to consider whether the 65C02 will continue to hum along when the speed changes or crash due to the resulting sudden change in timing.
The bulleted list of features at the top of page 1 of the DS1077 datasheet mentions "Frequency changes on-the-fly" and "Synchronous output gating." Did you overlook this, BDD? I know you're still recovering from eye surgery.
The 'C02 isn't bothered by speed changes, sudden or otherwise, provided that the PHI2 spec's for minimum tPWH and tPWL are met.
ETA: Hmm, apologies to our novice readers -- a better explanation is in order. With a WDC 'C02 you can flip the clock input , PHI2, high and low as quickly or slowly as you choose, and as regularly or irregularly as you choose, as long as you obey the following simple rule: Having flipped PHI2 high-to-low, or low-to-high,
you must wait 35 ns or more (the WDC part has no upper limit)
before you flip PHI2 again. IOW if PHI2 is high it must stay high for at least the minimum tPWH. If it's low it must remain low for at least the minimum tPWL. (Both figures are 35 ns, assuming 5 volt operation.) A runt pulse -- one that's too short -- can cause the CPU to crash or otherwise malfunction.
Runt pulses can arise when switching between clock sources. But the DS1077 is evidently designed in a way that avoids the threat.
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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