The (dodgy) WDC 816 datasheet suggests 5V is need at 14MHz. 8MHz is rated for 3V3.

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We've been doing this in the Pi world since the first Pi and while not perfect, I've not personally had issues driving 5v stuff from a Pi.



For low-speed stuff (say < 500Khz) and a small number of signals you can get away with resistor dividers (again, from Pi world experience), but faster and the signals degrade. The 74LVC245A is a popular choice though - you power it from the 3.3v side and put the 5v inputs directly into it and you get 3.3v out - the datasheet says it's tolerant of 5v inputs, so seems almost made for the job.

-Gordon
(edit to fix a silly typo)

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--
Gordon Henderson.
See my Ruby 6502 and 65816 SBC projects here: https://projects.drogon.net/ruby/

I guess there's no reason not to go with 3.3, I've worked with buffers in analog circuits before, and I remember reading about them on the primer (saw the word op-amp and was brought back to my cmoy days), so I suppose that won't be a hard thing to set up if I need the shifting. I'll be looking into 3.3v components for SRAM and such, see if I have better luck, I think I found a few parts already that were 2.7-5v tolerant, with 2.2 or 2.4v min output thresholds, I'm encouraged by hearing gordon used some of the chips I already found.

There is the point of the clock frequency from the data sheet though, and that may urge me to run at 5v, ofc, to start with I'm only trying for 1-4Mhz, so it shouldn't be a problem until my overclocking itch starts.

There has long been a suspicion that the WDC 65C02 and 65C816 have TTL-compatible inputs. In the case of the 65C02, it would make sense for that to be true, as the 65C02 is supposed to be a (nearly) drop-in replacement for an NMOS 6502. As an original circuit using an NMOS 6502 would have been built with 74LS silicon, it stands to reason the 65C02 would have to have TTL-compatible inputs in order to be compatible with the rest of the system. I was aware of several people in the past who had replaced the 6502 in PET/CBM machines with the 65C02, with success. That further suggests that the the 65C02, at least, has TTL-compatible inputs.

My first 65C816 unit used 74AC logic, no bus transceiver and directly connected SRAM and EPROM to the data bus of the '816. The 128K SRAM that I used generates TTL-level outputs, according to the data sheet. Operating at 5 volts, the unit is stable at 15 MHz. My latest unit has a bus transceiver and the CPLD circuitry is rigged up so it can be operated with "raw" outputs (TTL-compatible) or through a bus driver acting as a level converter. I'm hoping to determine—or not—that the 65C816 really has TTL-compatible inputs, despite what the data sheet says.

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This is very comforting, as from what I've found operating at 5v is a bit liberating for finding compatible devices, and I think it would be easier to shift down in voltage than up (can run only 5v rail and use one of the things mentioned in posts above to shift it to 3.3) I've got 3.3 power hookups in the schematic I'm working on right now, but I'll switch them to 5v, and maybe I can be a guinea pig for some of these chips to see if what you're saying is true.

Still though, I'm looking at using the bus transceiver circuit just to ensure no bus contention on the data bus, even if I want to push it up in speeds.

I've been reading through the topic that was linked by Garth earlier, and so far I've seen some discussion about the circuit in the docs being potentially wrong and dangerous because of timing overlaps from logic chips, I'm still reading further on it, but does it become a non issue with faster logic chips using the circuit in the docs? From what I've read, I think the consensus is that faster chips or no it can be problematic.

You might find the W65C265 interesting. It contains:
* 65816 cpu with more interrupt vectoring
* some chip select logic (with slower device options)
* 8 timers
* 4 UARTs
* 24 demultiplexed address lines
* monitor program in mask ROM (can be switched off to replace with RAM)
* a little RAM (the monitor can run with no external memory if needed)

Unfortunately it's only specced to 8MHz

The W65C265SXB is a nice & simple reference design.
It has a banked flash memory that it can boot from (the monitor does this automatically).
The flash can be switched off to replace with RAM.
It has a 32K RAM - but could easily increase to 4MB & beyond.

I may get one to play around with, but I'd rather stick with the 816 at the moment, as I'd like to work on learning the basics of layout and board design for this, rather than get a package that includes most of it.

The W65C265 is an IC and available in 68pin PLCC package and has the features leepivonka has listed. The W65C265SXB is a complete board that runs out of the box.

I know, what I mean is, I'd rather have completely discrete timers, memory, and rom as an exercise here.

On an unrelated note, I'm working on getting the top 8 bits of the 24 bit address bus off the 816, as I intend to have probably around 1M ram or so, since I might as well, like Garth mentioned.

After studying the circuit in the docs, I've been looking at these two parts here and here

One's an AHCT 245 and the other is a ACT 573 (non inverting).

I'm working out the logic on it right now, I think I need the non inverting 573, but there's an inverting one too, so I'm working on figuring that part out since it doesn't mention it in the docs.

Is there another part to this equation to make sure there's not bus contention?

The inverting vs non-inverting buffers doesn't matter. That's one of the cool things about SRAM. If it's not going to be used by anything but the CPU, you can invert and/or re-order the address lines however you please, and it'll just work. You can re-order the data lines, too, if it makes the layout easier.

Also, you don't need the -T parts unless you're getting an input from a TTL circuit. CMOS outputs work fine with TTL inputs.

Getting just a timer on a chip could be a bit interesting, although the VIA has two of them and a few other nice things in the one package.

After looking at BigDumbDinosaurs build on his website, I've been considering a discrete watchdog timer, it would give me delay capability too. Should I use the 6522 for this instead?

I hadn't considered a watchdog timer and I must confess I didn't look at all before I posted.

I've actually looked this time, and it looks like I was completely and totally wrong on the matter. (This is what I get for not looking before I open my mouth.) There are certainly watchdog timers available as discrete devices, and I see signs that standalone counter/timers are also available.

The VIA has a shift register, and 20 pins of IO(mostly general-purpose, but not all), as well as a couple of timers. It also sits on the 65xx bus.
I thought you were talking about a counter/timer, which is partially why I suggested the VIA. I also have this thing in my head that you need some measure of IO, but you don't necessarily...

I definitely want some io, planning on an acia and a via at least, and the 65spi chip I'm getting from Garth. I might add more if needed. My mem map is looking something like this right now:

0x000000
0x00CFFF -> RAM (52k)

0x00D000
0x00DFFF -> IO (4k)

0x00E000
0x00FFFF -> EEPROM (8k)

0x01000
0x40FFF -> RAM (large data, 4M)

0x41000 on, undefined.

I think this will work, but I've not looked at the binary yet to check bit assertions, thinking that it space may be a it tight, any suggestions from anyone?

You can use a timer in a 6522 as a watchdog timer too. See my post in the "Tip of the Day" column at viewtopic.php?p=2322#p2322 .

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What's an additional VIA among friends, anyhow?

Thanks for the tip. This may be cheaper than a discrete watchdog, and use less real estate. I've not looked up the watchdog chips yet. I figure I can use another timer on the 6522 for the "jiffy" timer for the machine.