What should I do with free inputs of PLD (ATF16V8)? Maybe, connecting to +5v... оr N.C... or there is some kind of their deactivation at programming...?

If those inputs are unused and not referenced in your code then they will be deactivated. Just make sure there is no reference to unconnected pins anywhere in your code.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Creating an address decoder on PLD 16V8 (or 22V10, not matter), the biggest problem, IMHO, is a lack of PLD inputs. One of possible solutions you can see on the picture below.
How to divide the I/O address space among the CS-outputs is up to you (and up to your PLD-program). The slight increase of [A9..15] propagaton time in 74HC00, IMHO, does not matter, the address information have nearly a half of clock cycle to get in time. In a pinch there is 74AHC30. What do you think, guys, about all this?

That 74HC30 is a slow device. Perhaps a better choice might be a 74ACT11030, which is some 15 times faster than the 74HC30.

Your need to add external logic to the GAL to make up with insufficient inputs illustrates why these devices have largely disappeared from the scene. In comparison, the Atmel ATF1504AS, which is the smallest CPLD that Atmel produces, has 32 uncommitted I/O pins, as well as considerably greater logic resources. Plus it's in a package that doesn't take up any more space than the NAND gate and GAL combined.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The other option is to chain 2 PLD's, a 2nd ATF device would also have a much better response than HC logic.

Hi Vladimir,

Looking at your diagram, I don't think you have the right address lines going in to the ATV16V8 to implement the address map you proposed.

You could move up to a 22V10 which would give you another 4 inputs.

But I think you can achieve you goal with just a 16V8.

It's possible in a 16V8 to use the Clock (pin 1) and OE (pin 11) and normal inputs, as long you you don't need to use any registers. In the data sheet this is referred to as "Complex Mode".

You would need to adjust your memory map slightly, and loose a few pages of ROM:

The pinout would then look like:

Dave

Hi Dave.
My design allows (if it is needed) flexible variations of I/O space size allocated to each of CS-outputs. For example, CS1 has 256 bytes, but CS2-CS5 16 bytes for each one. Unallocated space remains for possible expansion or relocation in the future.
How important is the accuracy of decoding - I do not know. Perhaps for programming convenience. If no one needs this , then, maybe, your circuit is better.

Vladimir

H Vladimir,

I don't think it's actually possible to implement the address map you proposed with the address lines you have going into the GAL.

Have you actually tried to write the logic equations yet?

At the very least, I think you need to move A9 from the 74LS30 to the spare input of the GAL.

Dave

Yes Dave. It is my fault, A9 really must enter into PLD, but not into 74HC30.
Equations may look like this:
ROM = A15 & !(TOP & !A9) & !(TOP & A9 & !A8)
CS1 = TOP & A9 & !A8 /* Page FE entirely, for example */
CS2 = TOP & !A9 & A8 & !A7 & !A6 & !A5 & !A4 /* 16 bytes from page FD, more precisely $FD00 ÷ $FD0F */
CS3 = TOP & !A9 & A8 & !A7 & !A6 & !A5 & A4 /* $FD10 ÷ $FD1F */
and so on... CS-outputs looks as active-high, but in pin-definitions they are defined as active-low, so that all will be well.
Really, I would have to write the equations before the scheme.
Additional chip (74HC30) only required for accurate decoding (for each register personal address). Let someone tell me wether such a need (accurate decoding) exists...

For such application, as address decoder, it is desirable 32 pins as well as considerably LESS logic resourses in order to have the price $0.4, but not $2. For each task must have suitable means. Maybe, ATF16V8 is not bad device, but not most suitable for my purpose? But, I have only such devices.

Hi Vladimir,

I think for a simple system a ATF16V8 is perfectly right. Of course it lacks PINs. But for a simple system this is not really the problem. The 74HC30 is a slow device, but for a 1MHz or 2MHz system this device is fast enough. Worst case delay is 26ns at 4.5V. This is fast in a 2MHz system. Your SPLDs have 15ns so this will give a total of 40ns worst-case. Your CPU is a 10MHz version so all signals will be settled well before the rising edge of PHI2. Nothing to worry about. However I suggest you use another decoder scheme, with the GAL16V8 being the primary decoder and using a 74HCT138 as a secondary decoder, although slightly slower (30ns versus 26ns) it gives you some additional free PINs on the GAL for future expansion and the mapping of ROM, RAM and IO Page only depends on the GAL and not on a fixed logic device (74HC30). You can also use the 74ACT138, which has only about 10ns delay. This decoding scheme has some advantages in case you want to change the mapping.



Cheers

Peter

Hi Peter.
It seems to me very strange that these two devices (74HC30 and 74HC138) have so small difference in propagation delay. 74HC30, NAND, as it seems to me , would be a basic element of the 74HCxxx series , i.e. the smallest building block for more complex devices. I read somewhere ( I do not remember where) that the 7404 chip contains six pieces of 7430 , and from each of them only one input is used. Another example - AND is in fact two NAND's connected in series. And so on. If we look at the internal structure of 74HC138, we can see that the signal passing from input to output , delayed at least by three or four elements. Therefore, considering the possibility of using 74HC138, I decided that it would be a very long delay , 3 or 4 times more than the 74HC30. So I chose the 74HC30.
Obviously, besides pondering, I have to look into the datasheets. I like your circuit. Thank you Peter.
By the way, I had a new headache. It is a question of compatibility TTL and CMOS. Datasheet of W65C02s says, that logic zero is less than 30 percent of Vdd and logic one is above 70 percent of Vdd. As I understand, this is 1.5 and 3.5 volts respectively (at 5v Vdd). The datasheet of SRAM 24257 says it is TTL compatible device (0.8 and 2.4 v respectively). I can not use 24257 ?

Cheers

Vladimir

Hi Vladimir,

the logical diagram is not necessarily what is electrically implemented and the delay of internal stages is much less then for stages with outputs. So in fact the 138 has only one internal logic stage more than a 30.

As for your RAM, the 24257 is a CMOS device and its outputs are high enough to interface with the CPU. I and others use all sorts of static CMOS RAM and did not have any issues. The RAM achieve normally an output well over 0.7VDD, potentially not at the guaranteed access time, but the additional delay is very small. Just go on and use your RAM

Cheers

Peter

The 65C02 was intended to be a drop-in replacement for the NOS 6502 and in fact, countless people have removed 6502s from Commodore PETs and VIC-20s and installed the 65C02 to take advantage of the latter's new instructions. These machines are all TTL (74LS) logic, which means the 65C02's inputs are able to correctly respond to TTL logic levels. CMOS devices are generally able to drive their outputs very close to ground and Vcc, so TTL devices being driven by the 65C02 will work fine.

The situation is less clear with the 65C816, and is clouded even more by the data sheet. In theory, the 65C816's inputs are CMOS compatible and hence would be iffy with a TTL device driving them. However, I've built three different computers using the 65C816 with an SRAM whose inputs and outputs are described by the manufacturer as TTL compatible—the data sheet says 0.8 and 2.4 volts for logic zero and one, respectively. That leads me to believe that the 65C816's inputs are TTL compatible, like the inputs of a 74ACT or 74HCT logic device, and those of the 65C02.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The non-WDC CMOS 65C02 were indeed drop-in replacements for the NMOS 6502, not the W65C02. You can clearly see that in the datasheets. E.g. when I look in the old datasheet of the G65C802/816 then minimal input high voltage for /RES, RDY, /IRQ, DATA, /SO and BE is 2.0V but in the datasheets for the W65C02/816 it says it is 0.7VDD for all inputs.

But nevertheless, even when using old EPROMs with the W65C816 in my older systems I never had any issues, however the highest clock I used in those systems was 4MHz.