akohlbecker wrote:
Unfortunately, the 65C816 requires an AC chip for at least the bank address latching as well as the associated logic, as the timing margin is pretty thin (10ns to latch after rising edge of clock).
74AHC logic will work as well in the latch application, as it typically has the prop times of 74AC but with less-aggressive outputs.
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For the RAM, go with a slow, 55ns one before attempting to increase the speed.
Why? The RAM's speed has nothing to do with circuit performance, unless the RAM is too slow. With most SRAM, output transition rate has little relation to the speed rating.
Incidentally, most contemporary SRAM has TTL-level outputs, not CMOS. If you use a bus transceiver in your 816 circuit it should be 74ACT or 74AHCT to act as a “level converter” (74HCT is not recommended due to its prop time).
74AHC logic is manageable on a two-layer PCB or a wire-wrapped unit, assuming good construction techniques.
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Having VDA, VPA be a part of the address decoding works but I would argue it is better to incorporate it into the read-write pulses.
No sir!
VDA and/or VPA is/are asserted midway during Ø2 low. At that time, the 816 will drive the data bus with the bank bits. Just how would using either/both of those signals to qualify read/write be helpful?
Asserting /RD during Ø2 low will cause severe data bus contention, making the system unstable at best, and DOA at worst. Asserting /WD during Ø2 low will create an opportunity for a wild write due to insufficient address bus setup time. During a write cycle, RWB goes low (according to the timing diagram) when VDA and/or VPA is/are asserted. However, that doesn't mean the rest of the hardware has “settled” following address bus setup. Also, asserting /WD before the rise of the clock means you are momentarily writing the bank bits to the addressed device, which is probably not a good idea.
Either reading and writing must be qualified with Ø2 or in lieu of such qualification, a bus transceiver must be used to isolate RAM, ROM and I/O hardware from the data bus whilst Ø2 is low. The “ideal” configuration is qualification with Ø2, along with a bus transceiver to deal with a small window of opportunity for contention to occur as the 816 “turns around” the data bus during a read cycle.
Caveat: nothing going to 65xx peripherals, e.g., 65C22, should be qualified by Ø2. Those devices “understand” the 65xx bus cycle and won't try to read or write during Ø2 low. In an 816 system, use of (as a minimum) VDA to qualify addresses to 65xx silicon is sufficient to avoid timing contretemps. Absolutely do not qualify addresses with Ø2. You’ll be disappointed with the results.
- Fully-Qualified Read/Write Circuit — can also be done with 74AHC logic
The board is intended for experimenting. You'll see locations for logic chips that only have power and ground connected. I'm then using pin headers to connect different configurations as I experiment. After I get something basic working, I'll spin a four-layer board with inner VCC and GND and cut down to the actual circuit I intend to use moving forward.
