Now, I'm reading over the 6502 primer and having trouble understand how clock generation works. What are the different phase clocks for and how come there isn't just a single clock pin like on the Z80? Is it possible to hook up a 555 timer at a few hertz to the 6502? because the primer has no mention of this.

As the local curmudgeon, the fundamental question is "What is the goal?".

Is it to get a chip to make blinking lights? A terminal connected to a monitor?

Why 8-Bit? Why not a modern micro controller?

Are you breadboarding or soldering?

There are several "minimal chip count" schematics available for both the 6502 and the Z80.

The singular advantage of a Z80 is that if you wish to go beyond "blinking lights", it's not that far to get CP/M and solid state storage on your machine, and, once there, you have access to a true bounty of software to run. 6502, not so much.

All of the processors (8 bit and modern micro controllers) suffer similar problems when it comes to dealing with decoding logic, peripheral interfaces, etc. No one is particularly "harder" than another if you stay "happy path" and use appropriate logic and support chips. Many microcontollers are "easy" as they need very few, if any, extra logic (which for many makes them less interesting from a "build a computer" point of view).

The 6502 and Z80 are still both produced, which is very helpful. Modern chips, modern standards. You're not salvaging something from a 30 year old machine.

The Z80 has a wider selection of tools to choose from also, both native and cross development. Not to say they don't exist for the 6502, just that there's more for the Z80.

There have been great wars raged over the advantages and disadvantages of one over the other, but in the end, it's probably more personal taste that will drive this decision. But, again, depends on your goals.

Something worth noting is that at any given clock speed, the 65C02 will handily out-perform the Z80. The margin is even greater when the 65C816 is considered. 65xx response to hardware interrupts is very fast, not so much with the Z80.

On the software side, I've always felt that the 65xx assembly language is intuitive and logical. As someone else once noted here, it's easy to envision solutions with 65xx assembly language. To me, the Z80 assembly language is obtuse, not unlike the x86 assembly language. When I see Z80 source code, I see a mess. When I see most 65xx source code, I see the flow of logic, even in source code with a paucity of comments.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Which is, more than likely, due to the fact that the Z80 was "loosely" based off the Intel 8080, IIRC.

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Cat; the other white meat.

Honestly, the goal of this is just to build a computer completely from scratch to understand the architecture. I was planning to use a breadboard and slowly add stuff like RAM and I/O as time goes on to see where that takes me.

A short history lesson may explain this.

In the 1970s, when the 6502 first appeared (there was also a 6501), the hardware available to generate clock signals wasn't nearly as robust as it is now. Circuits typical used a crystal oscillator, whose output was weak. So the 6502 was designed to accept the weak output of the oscillator and then produce "boosted" outputs for use by other parts of the circuit.

On the WDC 65C02, you have the PHI2 input, which receives the signal from the clock oscillator (which signal I refer to as Ø2 in my writings, the Ø symbol often used in electrical power generation to mean "phase"). Internal timing in the 65C02 is based upon PHI2. The 65C02 also has two clock outputs: PHI2O, which is the "boosted" form of Ø2, and PHI1O, which is the inversion of PHI2O. Succinctly stated, when PHI2 is high, PHI2O will be high and PHI1O will be low.

The 65C02 as designed was intended to be a "drop-in" replacement for the NMOS 6502. As much 6502-powered hardware of the past makes use of PHI2O and PHI1O, the modern form of the 65C02 continues to have these outputs. These days, new designs mostly utilize "can" oscillators that are able to generate a strong and reasonably symmetric clock output that readily services the microprocessor (MPU) and other system devices, such as a 65C22. Hence the need for PHI2O and PHI1O has markedly decreased. In fact, WDC's data sheet for the 65C02 recommends that the PHI2O and PHI1O outputs not be used in new designs, as the relationship between those signals and PHI2 (the clock input) is neither specified or tested:

3.8 Phase 2 In (PHI2), Phase 2 Out (PHI2O) and Phase 1 Out (PHI1O)

Phase 2 In (PHI2) is the system clock input to the microprocessor internal clock. During the low power Standby Mode, PHI2 can be held in either high or low state to preserve the contents of internal registers since the microprocessor is a fully static design. The Phase 2 Out (PHI2O) signal is generated from PHI2. Phase 1 Out (PHI1O) is the inverted PHI2 signal. An external oscillator is recommended for driving PHI2 and used for the main system clock. All production test timing is based on PHI2. PHI2O and PHI1O were used in older systems for system timing and internal oscillators when an external crystal was used.

Also:

Timing Notes:

1. Timing measurement points are 50% VDD.
2. PHI1O and PHI2O clock delay from PHI2 is no longer specified or tested and WDC recommends using an oscillator for system time base and PHI2 processor input clock.

The bottom line is in a new design, you would not connect PHI2O or PHI1O to anything, and derive your clock signal solely from the "can" oscillator. If you use the PHI2O and PHI1O outputs, the circuits being driven by them will lag PHI2 by an unspecified amount, which may create difficult-to-resolve timing issues.

As for using a 555 timer as a clock source, it will work, although achieving a reasonably symmetric clock may be a challenge. A low speed oscillator using a comparator may be better.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Very well said, BDD.

Something else I'd like to point out is that the Z80 world has CP/M. Which is an asset that I wished the 6502 world had.

HOWEVER, I personally feel that to really get good use out of CP/M, you need much more than the 64K the Z80 is limited to (the 6502 is also limited to 64K). So in order to make CP/M shine, you need a more advanced computer with 128K, 512K, etc. Which means more bank switching, more decoding logic, etc.

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Cat; the other white meat.

My apologies if this isn't the clearest it could be. I have a lot of work to do today and I'm in a hurry.

For simple systems, phase 2 is all you need. The primer's clock-generation page gives a few clock options. I'm not sure the 555 will have adequately fast edges (ie, how quickly it gets from high to low, or vice-versa, regardless of frequency) for the 65c02's being produced today. A couple of members here ran into trouble with inadequate slew rate when using WDC processors. Also, heed what it says there about non-WDC 65c02's needing to stay below a certain maximum time on the phase-2-low time, meaning you would not be able to use a 1Hz square wave for example. (The WDC ones can be stopped indefinitely with phase 2 either high or low; but other brands can only be stopped with phase 2 high.) There's a circuit there for single-clocking which lets you stop indefinitely in any cycle, but only with phase 2 high, and the phase-2-low time stays below the maximum allowable time for Rockwell, CMD, Synertek, and other manufacturers. For an oscillator, a crystal oscillator can is usually the best way to go. The circuit at the top of the circuit potpourri page shows different clock options too. The notes below it tell what you need to know (particularly Note 1 in this case). Someone suggested separating out the different options of that part of the diagram, with individual very small diagrams of just the clock circuit, and offered to do it for me so I could edit the page and insert this part with less work; so that may be coming.


I do not encourage using solderless breadboards for this kind of work. Many people do it, and more than half of these creations work, but that still leaves an awful lot that don't work, and an awful lot of frustrated builders. One of the chapters in the primer is about wire-wrap. Unfortunately WW supplies have gotten more expensive in the last ten years; but you can certain get a circuit that's better behaved with WW. A custom PCB is best (assuming it's laid out well), but not everyone can go that route. None of the chapters in the primer are frivolous. I put a lot of time into making it as concise as I could, answering questions and problems that kept coming up on the forum years ago, and I frequently make little edits to improve it. The sections are also organized more or less in a logical order; so I recommend going through it that way, including paying attention to the section on avoiding AC performance problems. That way if you do feel a solderless breadboard is your only option at this point, hopefully you can still do it in a way that will get working results.

Best of luck, and again, my apologies for having to punch this reply out without taking the time to make it more clear.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

If that's the goal, then use the 6502.

Why?

Because you have Garth's primer and this forum.

There's isn't a forum comparable to this one. So, any problems you might encounter, you'll find expert help here.

You can always use the skills learned from building a 6502 to build pretty much anything else later on.

So, I have a 6502 processor in hand. Should I try wiring up a NOP test? Also, how would I go about making a single step clock signal with any kind of de bounce so that I can observe that the address lines are counting up with led's?

With regards to the logic chips, I intend to order an assortment of them so that I will have them on hand when I need them. Which ones should I get?

Thanks,

That would be the quickest and easiest way to prove your circuit is working.


Garth has such a circuit on his website at this page. Scroll down to see it.


It depends on your circuit design. My recommendation is to use 74AC or 74HC logic. 74HC is "better" for what you are trying to do, as its switching speeds are not as fast as 74AC, which will make your design more tolerant of dubious construction methods.

It's best to not use 74S, 74LS or 74ALS, as these logic families are not CMOS-compatible and also tend to consume quite a bit more power than CMOS devices.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I would put the 74HC00 quad 2-in NAND at the top of the list, followed perhaps by the '04 inverter, '02 quad 2-in NOR gate, and '14 Schmitt-trigger inverter. The '138 3-to-8-line and '154 4-to-16-line decoders are always tempting to the newbies, but their propagation delays are quite long, and the fine-grained address decoding they are usually desired for comes with a speed penalty. The '245 octal tri-state transceiver may come in handy at some point. I have lots of others accumulated over the years, but that's not to say you need to start with them. Ideally, data books, yes, actual paper, would still be available, and you could look through the various and highlight the most useful ones, possibly in different colors for different functions. You can still find such indexes online though, and print them and do this. If you're wondering about certain parts, come back and ask.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for the input everyone! Ok, so I salvaged a NMOS 6502 out of an old piece of equipment just so I can play around with it for a little bit but I intend to purchase a new WDC cmos variant later on.

So what I did is hardwired the 6502 in NOP mode and hooked A0-A6 to the data pins of my arduino and used one of the data pins as a clock. I wrote this bit of code:



It does 2 clock cycles before reading off the address bus since 2 clock cycles are needed to complete the NOP instruction.

So I just read off the address bus and printed the output to the serial monitor and got something like this:



Which looks to me that it is counting in binary, however, it doesn't start at EAEA, but a little bit higher than that. Why is that?

Hi, qwertykeyboard

In fact it *does* start at $EAEA but you're not seeing that very first cycle because this procedure you're using is slightly misguided: "It does 2 clock cycles before reading off the address bus since 2 clock cycles are needed to complete the NOP instruction." Instead, try reading off the address in the first cycle. Here's why.

With 65xx processors all opcodes are a single byte, and sometimes an instruction will have one or more operand bytes following the opcode. For performance reasons the processor always follows the opcode fetch with a fetch of the following byte, and often this saves time. NOP is one of the exceptions, however, as there are no operand bytes following the opcode. But the extra fetch happens anyway.

So! After having fetched the Rest Vector the CPU goes to $EAEA to find its first instruction. It fetches the byte at $EAEA, which is the opcode. It then fetches the byte at $EAEB while the NOP completes its execution. But this fetch is actually pointless because there's no operand. After the NOP has completed the CPU will go looking for the next opcode... at $EAEB! IOW it fetches that same byte again. This same pattern repeats endlessly, with the address bus incrementing after the 1st, 3rd, 5th cycle and so on. I hope I explained that so it makes sense!

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Current versions of the 74HC138 typically achieve prop times in the 10-15ns range on 5 volts, which is way more than is needed in a system running at a couple of megahertz. For faster units, the 74AC138 routinely achieves single digit prop times on 5 volts. For example, ON Semiconductor rates their 74AC138's tPLH at 6.5ns typical, 9.5ns maximum. My POC V1.1 unit uses a 74AC138 to decode I/O and will boot at 15 MHz if the SCSI host adapter isn't installed.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!