BigDumbDinosaur wrote:
Regarding SRAM control, I know Garth's primer shows a circuit in which /CS is qualified by Ø2. The problem with doing it that way is you lose part of Ø2 low when you could be doing your setup. You should gate /CS as soon as a valid address is on the bus, which occurs approximately midway during Ø2 low on the 65C02 and 65C816.
The reason I do that is not just simplicity, but that SRAM is available in faster speeds than anything else you'll put on the bus, down to 6 or 8ns access time, so it doesn't need the extra time. Now if you're using old 450ns RAM at 1MHz or higher, then yes, you better get it started before Φ2 rises.
Quote:
What does need to be qualified by Ø2 is RWB, as allowing a write when Ø2 is low can have undefined effects, especially when access I/O hardware. The data bus contains undefined content during Ø2 low. Qualifying reads and writes with Ø2 addresses that matter. See attached for an example circuit.
The big problem with allowing writes before Φ2 rises is that the
address bus is not guaranteed to be valid and stable before R/W\ goes low, so you might write to an unintended address. According to the processor data sheet, the data is not valid yet when Φ2 rises; but for a legitimate address, as long as the data is valid and stable before the RAM's setup time before Φ2 falls at the end of the cycle and the RAM is de-selected, you're ok. This might be more than 3/4 of the way through the cycle.
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If your problem is hardware-based then you may have a glue logic error. Otherwise, I'd have to go with the other guys and question your program.
