GARTHWILSON wrote:
Welcome. Let's hear those "crazy ideas." Crazy ideas are often DOA; but other times they're the kind that make me say, "That's ingenious! So simple, and yet a perfect solution! Why didn't I think of that?!" Even now, closing in on 50 years after the introduction of the 6502, I expect there are still great techniques, especially in software, that remain to be thought of, or at least published.
Hi Garth,
there are a huge quantity of 3D and very interesting articles in your website and in this forum, it's no easy for me to find specific argument.. but I will try in the next year
In the meantime pardon me if I ask infos about my first curiosity: sharing RAM with external device, to allow pseudo "transparent" use of one intelligent HMI.
In the past I solve this job with dual port RAM (see attachment) but hardware implementation is not cheap; I remember that old Commodore machines share part of system ram with video device (VIC 6561)
Well, in your opinion should be possible to manage system RAM during PHI2=0 when 65C02 dont access to RAM/ROM ?
For example, with one system board that run 65C02 at 1.8432 we will have:
- PHI2 active more or less for 270 nS and inactive for similar time
- PHI1 active for 270nS , alternate to PHI2
- we dont permit access bus for 50 nS from PHI rising to avoid overlap on systemn address/data bus
Teorically - with 70nS RAM - we have more than 100nS to read or write 1 byte of RAM (obviously non cuncurrent writing, unsemaphored and asinchronous data exchange require use of 2 separated memory block..)
I suppose that this opportunity was already discussed, do you have memory of that ?
Thank you in advance !
maurizio