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PostPosted: Fri Jan 28, 2022 6:12 pm 
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CMOS inputs should not be allowed to float!
Just a reminder that that applies to MOS inputs as well as CMOS inputs.

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PostPosted: Sun Feb 27, 2022 2:20 pm 
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Regarding long chains of 74x161 and similar, I really wonder what people are doing with 12 or more units. Starting at zero, 2^48 bits of counter clocked at 25MHz takes 130 days to wrap around. The first two units are wired in a special manner to permit high speed counting. The remainder is never an issue. Pessimistically assuming that inhibit signals propagate at counting frequency, everything works correctly across 12 or more units.

sburrow on Thu 30 Dec 2021 wrote:
I was going to to use 2x2 pixel 'blocks' anyways.


Don't stop at even pulse widths. See how far you can push it. I planned to make horizontal sync and horizontal porches which are always a multiple of 16. That would allow 1920*1080*60Hz video with 16*16 pixel tiles where only the shift register has to operate at 150MHz. Everything else runs below 10MHz. Using this technique, it may be possible to quadruple the dot clock while keeping the majority of the circuit below 40MHz.

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