Hello everyone, and Merry Christmas! In between church, kids, toys, and all that, I manage to find some alone time once in a while

This is a short question. It is related to some other projects I'm working on.

Attached is a picture of part of my schematic. I have 3x 74HC373 latches, and the 1x 62256 SRAM. Two of the latches have the addresses, and one latch as the data. They are all connected to a common input bus (on the 6502 side of things). I want to use them to write a byte to this RAM.

The procedure is to load the data into the first latch, then the second latch, then the third latch. Finally, I drive the /WRITE line low, which allows the latched data to travel to the RAM, and also enables the RAM's /WE pin. But what about the /CS pin? See, the data in the latches should take some nanoseconds longer to reach the RAM. If I had the /WRITE line also connected to the /CS line, the RAM would open up for writing, but the data from the latches won't yet be activated, so I *could* write random information to random places. Correct?

So I added a double-not gate, giving the latches time to propagate, and THEN the RAM writes what's on the bus. Is this a good thing to do?

I have 62256 RAM which is kind of slow, but lets say I had some 20ns SRAM or something. I don't know, just theories. Would I then need to slow down the /CS line at all?

We could switch the /WE and /CS pins of course, or I could just keep /CS low and use only the /WE pin instead. Either way, how do I make sure the RAM doesn't get spurious data written to it before the latches have time to send their data?

Thoughts?

Thank you everyone!

Chad

Can you leave the outputs enabled on the address latches then read or write RAM directly using the data lines, /CS, /RD (/OE) and /WR signals?

Good question!

No actually, I should have also stated that I am using this RAM for other purposes too (but not a processor on this side of things). I'm reading from it (thus the /READ line I have).

So, when something is not reading from it, I will generally be writing to it. But if something wants to read from it, it's off limits to my writing. Thus these particular latches with their /OE lines help a lot.

Thank you Michael.

Chad

EDIT: The /CS line would of course have to share with the other stuff reading from it. Or I could just leave /CS low and let /OE and /WE do their thing. Either way, there is something else wanting to use the RAM.

Using 2 inverters as delay line so RAM addresses & data are stable before RAM chip select is asserted is somewhat dangerous because this is a race between RAM, latch, and inverter. However, it should work. The slow RAM actually helps you because it may ignore fast glitches. Fast RAM can be more troublesome.
Bill

Thank you Bill.

It's hard to test this, because of course it would write to the location I'm thinking. But it might also write somewhere else, something else. I might not know I have an issue until I start seeing random little issues here and there later down the line.

I am thinking of using faster RAM. I found that the 71256 yesterday, never knew it existed! And that is 20ns.

Thank you again.

Chad

EDIT: I did a lot of datasheet diving, drew pictures, and did some math. I'm now looking in particular at the 71256 SRAM, which claims 20ns.

T=0, /CS or /WE on RAM falls, and also the /OE on the '373 falls.
Time for RAM to write from the falling of /WE or /CS is 15 ns.
The data must be on the bus for 11 ns before that, thus 4 ns after T=0.
The latch opens up around 20ns (could even be 30ns!).

So now the data that should be ready at 4 ns after T=0 is actually ready 20ns after T=0. That's not good.

Each NOT gate is 10ns. So lets redo the timing, with a double-not to the RAM to move it out some. I'll just keep /CS low and use /WE in this case.

T=0, /OE on '373 falls, at the same time it falls on the first NOT gate.
T=10ns, /OE turns into OE on first NOT gate, travels to second not gate.
T=20ns, latch data opened up on bus, also OE turns into /WE on the second NOT gate, so /WE on RAM now falls.
T=24ns, RAM needs valid data, which it now has.
T=35ns, RAM finally writes the data on the bus.

If the latch goes to 30ns it's not going to work, but it says typical is 20ns?? Who knows.

Whelp, I think I'll just keep /CS low and let /OE and /WE do the work.

Thank you all.

You need to check the datasheet for the particular RAM you're using to get the precise timings, but in general the write starts when both CE and WE are low. The address lines should be valid and stable for a certain time before that condition occurs to prevent spurious writes to unintended locations. The actual data to be written doesn't need to be valid at the same time; instead it should be stable for a certain time before either WE or CE goes high. Also, there is a minimum low pulse width for CE and WE, which can be found from the data sheet.

I usually hold CE low permanently - that gives the best performance since the address begins to percolate through the device as soon as it becomes valid. On the other hand, that does consume more power, which might be a consideration depending on your application.

Yes, at this point I think I'll just hold CE low and use WE to control writes.

If there is even more time that the addresses need to be stable beforehand, that sounds like even more double-not gates. Which, as Bill stated, is dangerous.

Thank you.

Chad

If address/data/read_write are generated at rising edge of clock, then you can tie the 2nd half of the clock (clock low) to RAM's chip select. By then address/data/controls are stable.
Bill

Hm!

That is an excellent observation. So this particular '373 uses the high and low inputs, but I think there is an 8-bit latch that uses the clock's rise or fall. Something to consider for sure! Thank you for that.

Chad