Druzyek wrote:
BigDumbDinosaur wrote:
A 10ns CPLD, such as an Atmel 1504AS, will readily support the fastest 65C02
Is this the model you would recommend? I was considering Atmel GALs but it seems from the forum that they are hard to program. I would rather not buy an expensive programmer. If there is a cheap board that I can program the chip over USB with or documentation of the protocol so I can build a programmer (which I have done before) then that would be ideal.
Atmel's GALs have a programming algorithm that doesn't appear to have widespread support. For GALs, track down Lattice parts, which are readily available from eBay sources.
On the other hand, Atmel's 15xxAS CPLDs are "industry standard," in that they may be programmed with Atmel's test rig (which I have) or via a suitable JTAG setup. Atmel offers WinCUPL for writing your code, which ultimately gets compiled to a standard JEDEC fuse map that can be burned into any PLD that uses that format. Hence you could use WinCUPL to write code for a Lattice GAL.
My POC V2 unit, which is currently on the "drawing board," will use an Atmel 1504AS CPLD in a PLCC-44 package for the glue logic. Said logic will include memory mapping for a single 512KB SRAM, as well as the customary chip selects for RAM, ROM and I/O. The design will also include wait-stating for ROM and I/O, since a goal of this design is to support 20 MHz operation. The irony is that the PLCC-44 package takes up only a little more space than the PDIP-24 package of a 22V10 GAL, yet the 1504AS has far more logic capability.
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You could also consider using a GAL
This sounds good. How much logic could I fit into one? I would also need one that could be easily programmed (ie no high-voltage or expensive programmers) If I do try to do the complicated memory mapping I suggested, it would be something like this. Do you think it would fit?
Code:
if A15-A11 = 0000.0 then output=0000000001 'enable 0 bufffer
elseif A15-A6 = 1111.1101|11 then output=0000000010 'CS bufffer
elseif A15-A6 = 1111.1110|00 then output=0000000100 'output buffer
elseif A15-A6 = 1111.1110|01 then output=0000001000 'input buffer
elseif A15-A6 = 1111.1110|10 then output=0000010000 'low buffer
elseif A15-A6 = 1111.1110|11 then output=0000100000 'high buffer
elseif A15-A8 = 1111.1111 then output=0010000000 'enable ROM
elseif A15 = 0 then output=0100000000 'enable low buffer
elseif A15 = 1 then output=1000000000 'enable high buffer
Something along those lines would work with a 22V10 GAL (10 outputs). You need to do some reading on the standard GAL series and what they offer in terms of logic capabilities and I/O pins. At the time when GALs were riding high, many companies produced interchangeable parts, such as 16V8, 20V8, etc. The data sheets are still readily available.
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Also, from Garth's page it seems that there are some speed penalties for running at 3.3v. Would you recommend just running everything at 5v to make things easier?
In general, CMOS performance is a function of operating voltage. The relationship between Vcc and Fmax (maximum operating frequency) is graphically described in the WDC product data sheets—look on page 24 of the 65C02 data sheet to see the graph. The Vcc vs. Fmax curve for the 65C02 indicates that 14 MHz is possible at 3.3 volts. Stepping Vcc up to 5 volts increases Fmax to (it is implied) well over 20 MHz. It's your call. I chose to run my POC units at 5 volts so I could use standard 27Cxxx EPROMs and other standard I/O hardware. Going with 3.3 volts may close some doors but open others (larger SRAMs are 3.3 volt parts, for example).
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For ROM speed, is it just phase time - tDSR - decode? 70 - 30 - 10 = 30ns for 14MHz? For writing to RAM, is it phase - 20 (min time before phi2 goes down) - decode? 70 - 20 - 10 = 40ns for 14MHz?
A simplistic way to state the timing goal is to say that the addressed device must accept or output data before the fall of the Ø2 clock during a valid read or write cycle. There's a bit more to it but that is a starting point. So what you can do is work your way back from the fall of Ø2 to determine the level of performance that the glue logic and addressed device must achieve. Let's suppose the Ø2 rate is 10 MHz. Hence the duration of each phase of Ø2 is 50ns, assuming a symmetric clock.
In studying the 65C02 timing diagram, it is understood that the MPU places a valid address on A0-A15 no more than
tADS nanoseconds after the fall of Ø2. That number is listed as 30ns maximum if Vcc = 5 volts, which means that A0-A15 will be valid 30ns before the rise of Ø2 (however, see my digression below). At that time, your glue logic would get to work generating the appropriate chip select for the addressed device. The glue logic, of course, adds gate delays (prop time), so the relevant chip select doesn't get asserted until
tPROP nanoseconds after
tADS, where
tPROP is the cumulative delay of all gates involved in the selection process. Let's suppose
tPROP is 10ns for the sake of argument, implying that you are using a PLD (10ns via cascaded discrete logic is essentially not achievable). That being the case, the chip select will be asserted
tADS+tPROP nanoseconds from the fall of Ø2, which is 40ns. Looking at it a different way, chip selection will not occur until 60ns before the next fall of Ø2, which is our ultimate reference point, since D0-D7 must be valid (read) or will be stable (write) before that point in time (I'll get to that in a minute).
Now, even though the addressed device's chip select has been asserted we don't yet have a "connection," as the device itself exhibits some delay from when it is selected until it is ready to accept or output data. Let's say that device is a 27C256-55 EPROM (fastest erasable version of the 27C256 series available from stock), which is what I use in my POC V1.1 unit. The EPROM's "access time" is 55ns, which is defined by the symbol
tCE. What
tCE means is that the device will take up to 55ns to respond following assertion of its
/CE (chip select) input. This is a worst-case number, of course, but must be considered in designing a circuit that will reliably operate in a variety of temperature and voltage conditions. Hence the EPROM isn't guaranteed to respond until 5ns before the fall of Ø2, which is cutting it uncomfortably close.
DIGRESSION: Some of WDC's timing figures seem to be unworkable when considered in terms of how fast the 65C02 and 65C816 can be operated. A number of us are of the opinion that the 30ns tADS number is clearly bogus, as devices such as CMD's SuperCPU cartridge for the Commodore 64, which operated its 65C816 at 20 MHz, would not have functioned if tADS = 30ns were true. Also, my POC V1.1 unit runs reliably at 15 MHz, which the timing analysis says is impossible if tADS is actually 30ns.
Also to be noted is the delay that occurs from when the address inputs of the 27C256 are asserted until it exposes the correct memory cell to the data bus. This delay is defined as
tACC and is listed as 55ns as well. Since A0-A15 is valid before
/CE is asserted (due to
tPROP),
tACC will be satisfied before
tCE and can be safely ignored.
The other EPROM input that glue logic must control is
/OE (output enable), which must be asserted before the EPROM will actually drive the data bus. As with
/CE, some delay will occur after
/OE is asserted before data will appear, which is defined by the symbol
tOE, which for the 27C256-55 is 35ns. As all read/write activity on non-65xx silicon should be qualified by Ø2 to avoid glitches (especially important with the 65C816, which uses D0-D7 to generate the memory bank address during Ø2 low), the reference point for
tOE is the rise of Ø2. Since each clock phase is 50ns in duration, the earliest that the EPROM could be made to generate output would be 35ns after the rise of Ø2 or 15ns before the next fall. Hence the logic that qualifies RWB must assert
/OE in less than 15ns if the EPROM is to put data on the bus before the fall of Ø2.
The WDC specs say that data must be valid
tDSR nanoseconds before the fall of Ø2, that is, 10ns. In reality, that number can be (probably is) smaller than specified, as the MPU samples D0-D7 on the fall of the clock. Once the EPROM is driving the data bus your circuitry must satisfy the MPU's
tDHR hold time, which elapses 10ns after the fall of Ø2. Hence the
/CE and
/OE inputs to the EPROM must be maintained for the
tDHR period to assure that the MPU will reliably read what's on D0-D7. As it turns out, the EPROM maintains output for a short period of time after
/CE and/or
/OE are deasserted, which is described by the symbol
tDF, and is specified as 25ns for the AMD EPROM that I am using. Hence the EPROM takes care of satisfying
tDHR.
As you can see, it's not complicated, just some addition and subtraction. Understanding timing characteristics is key to successfully designing a circuit that will run fast. As Garth once point out, you can get away with murder at 1 MHz. Higher speeds won't be as forgiving.
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Edit: fixed two typos.