Hi,
I'm trying to implement this memory map in my 6502 computer:

But it's not working, i have program to display $55 on port A on 6522, but i'm getting on it garbage (when i reset cpu i see difrent garbage on led's), cpu insted of jumping and staying at $C002 keeps going to $F--- (i cant get rest of addres line it changing too quick). When i plug data line to my osciloscope i see this thing:

it dont look like normal digital signal. I also have 3.3 to 5v converter to pull select pins of eeprom 28c256 and 62256 ram.
Code look like this:

.segment "BEGIN_PROGRAM"

reset:
lda #$ff
sta $A002

lda #$55
sta $A000

loop:
jmp loop

.segment "RESETVEC"
.word $0000
.word reset
.word $0000

I have IRQ and NMI pulled high by resistors.

And here is HDL code i have on my 7032:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ezPLA is
port(
a13: in std_logic;
a14: in std_logic;
a15: in std_logic;
clk: in std_logic;
clk2: in std_logic;
a12: in std_logic;
RAM: out std_logic;
TMS9918: out std_logic;
H6551: out std_logic;
L6551: out std_logic;
H6522: out std_logic;
L6522: out std_logic;
YM: out std_logic;
ROM: out std_logic
);
end ezPLA;

architecture rtl of ezPLA is

begin

process(a13, a14, a15, clk, clk2, a12)
begin
RAM <= not ((not a15) and clk);

TMS9918 <= not (a15 and (not a14) and (not a13) and(not a12));

H6551 <= a15 and (not a14);

L6551 <= not (not a13 and a12);

H6522 <= a15 and (not a14);

L6522 <= not (a13 and (not a12));

ROM <= not (a15 and a14);

YM <= (a15 and (not a14) and a13 and a12) nand clk2;

end process;


end architecture rtl;

Hello, Chini_fox.

In order to help, we need more information. You're telling us about the part where you think the problem is, but your focus may be misplaced (and that may be why you're stuck). And you're leaving out some VERY BASIC INFORMATION such as the schematic, and some photos of your project!

Uh... do you think it might help if you could told us which data line? Please try again, and don't be in such a hurry.

BTW, on this forum you're allowed to attach photos to your post. I look forward to seeing what you're up to!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

There may be other issues, but VIA registers 0/2 are Port B, not Port A.

Dave

I probed data bus, over YM3812, I dont have schematic, but i make this picture, i hope it will show how computer is wired up, (I hope photo will be visible)

Blue wires are data bus, and green ones are address bus, you can see A15-A12 going to CPLD, and also clock (RAM timing) and clok2 from 6502 (timing of ym3812),
orange wires are chip select for 6522.
For ROM and RAM i'm using 3.3 to 5v converter (they are CMOS so i think they need higher voltage to be active), on ROM i also have A14 pulled down to work in $0000-$3FFF addres area of EEPROM, and it's mapped to C000-FFFF of 6502.
I also have D flip/flop for decoding R/!W signal for tms9918,
blue wires are ones that select UART 6551.

here is powered up computer, you can see that insted of reading from c00- it read's from F---.
Before i have glue logic from 74 series chips, and it was working fine.

Hello again! And thanks for the photos.

I still have lots of questions. And BTW I hope you noticed the point that Dave (Hoglet) mentioned.

I'm pretty sure the voltage converters are not necessary. The ROM and RAM are not the same as logic chips such as the 74HC series. Even though the ROM and RAM may be fabricated in a CMOS process, chips like that usually have inputs that accept TTL voltage levels. I believe this is true for 28C256 and 62256. I haven't checked those datasheets, but the answer will be there.

BTW, is your CPU an actual 6502 (ie, NMOS)? Or is it a 65C02, from Rockwell perhaps, or WDC?

Sorry, I don't understand. A SCHEMATIC would be really helpful!

I know you said the project was working fine when you had 74 series chips for the glue logic... and the trouble started after you replaced the 74 series glue with the 7032 PLD. But we cannot be certain the trouble came from the 7032.

There are several other possibilities. For example there may be a problem with bad connections... connections which were OK for a while but then got disturbed when you made the wiring change. (Solderless breadboards are notorious for unreliable connections. )

That is why we will have questions about many subjects... not just the 7032.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I don't have anything helpful to offer, I'm afraid, but I am curious about that PLCC socket. How did you attach that to your breadboard? I have a couple of PLCC breadboard adapters, but they're enormous! It looks like yours is plugged directly into the breadboard, or if there is an adapter under it, it is very tiny!

_________________
"The key is not to let the hardware sense any fear." - Radical Brad

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Sorry, i'm dumb, i just connected chip select that was suposed to go to mos 6522 to wrong pin (chip was always active and becouse of that i got garbage on data bus). I've been siting on it for 4 days and it was just this simple mistake.

Sorry for creating this post, i'm too much zoomer, should i delete this post or somehow close it? It's realy first time i'm using forum.

Hi Chini_fox, no need to be embarrassed or any need to modify the thread. It's completely normal to have made a mistake, and to find it and correct it. It's one of the lessons of electronics as a hobby - the distance between the thing you intend to build, and the thing you did actually build. There are many possibilities for divergence.

Only by careful checking, sometimes measuring, sometimes formulating hypotheses and experiments, can you find out what has happened and correct it.