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Verilog to WinCUPL generator\workflow
http://forum.6502.org/viewtopic.php?f=10&t=7601		 Page 1 of 2
Author:  mike9repeating [ Sun May 14, 2023 4:43 am ]
Post subject:  Verilog to WinCUPL generator\workflow
Hello,

To anyone who may be interested, I've come up with a handy way to generate WinCUPL from Verilog using Yosys and a simple utility I wrote called JsonToCupl. You can find this utility on GitHub https://github.com/michaelhunsberger/JsonToCupl. Yosys is a free and open source tool for digital logic--It really does all the heavy lifting. My tool just is just a simple code generator.

The process is as follows:

1) Use JsonToCupl utility to generate a ".ys" script.
2) Execute the script using Yosys. This generates a json file that represents the design. The design is flatten and optimized to primitives like NOT\AND\OR\XOR\D-Flipflops\Latches. These primitives are easy to convert to WinCUPL.
3) Execute JsonToCupl again, supplying the json script. Creates WinCUPL expressions\pins\pinnodes. This final step generates the PLD file.

Some background:

I wanted to program older logic but wanted to use a more updated HDL than WinCUPL. I know there are commercial solutions to target older 5v chips (Pro Chip Designer?) but are not free (I think its if you have to ask, you can't afford it). I used another solution in the past using an old version of quartus and another tool called POF2JED, but this resulted in unstable\bad results. Sticking with WinCUPLs synthesis was the way to go.

The generated code is ugly, but so far, my testing has shown it to work. I included 2 examples, a UART and a ripple carry adder. I was able to get the UART onto an ATF1504, the adder was able to fit onto a AFT22LV10C. I tested the UART by feeding the rx into the tx port and using a simple terminal to view the echoed characters.

If anyone knows of other alternatives, I'd love to hear about it! I originally did this for a 68000 project I was working on, but never completely finished. In that project, the all the glue logic was done on a single AFT1508. Hoping to someday finish that.

Thanks,

Mike.

Disclaimer: I am just a hobbyist, and I'm not an expert on Verilog or WinCUPL.
Author:  BigEd [ Sun May 14, 2023 7:13 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
Sound like a handy tool - thanks for sharing! (And welcome!)

(It might be particularly useful to be dealing in CUPL format that's very much of a certain type: if it works at all it should work for all kinds of cases.)
Author:  hoglet [ Sun May 14, 2023 7:42 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
mike9repeating wrote:
Hello,
If anyone knows of other alternatives, I'd love to hear about it! I originally did this for a 68000 project I was working on, but never completely finished. In that project, the all the glue logic was done on a single AFT1508. Hoping to someday finish that.

Coincidenally, I also had a go at this a few months ago:
https://github.com/hoglet67/atf15xx_yosys

The tools flow here is:
- Yosys plus a custom ATF15xx technology library, to convert Verilog to an EDIF gate level netlist
- WinCUPL fitter, to convert the EDIF netlist to a JEDEC file

I have both of these steps running on Linux (the WinCUPL fitter using WINE)

There are some brief getting started notes here:
https://github.com/hoglet67/atf15xx_yosys#readme

I think the main difference between my approach and your approach is the intermediate format: you used CUPL and I used an EDIF gate-level netlist.

My main contribution was to develop a Yosys Technology Library (in Liberty format) that contains the set of gates and registers that WinCUPL expects to see in a gate-level EDIF netlist. This closely mirrors the way that the paid-for version of ProChip Designer uses the Mentor synthesis tools to support verilog design entry with WinCUPL. Except Mentor Precision Synthesis is replaced by Yosys. As fas as I could see, the end results were quite similar (in terms of product term usage).

You can see the technology library (in liberty format) here:
https://github.com/hoglet67/atf15xx_yos ... /cells.lib

This is quite large and repetive, so was generated by a short C program:
https://github.com/hoglet67/atf15xx_yos ... ools/gen.c

This script contains the yosys commands needed to use the library:
https://github.com/hoglet67/atf15xx_yos ... n_yosys.sh

Dave
Author:  hoglet [ Sun May 14, 2023 11:21 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
(above post edited to add a bit more detail)
Author:  Proxy [ Sun May 14, 2023 8:12 pm ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
on the github, the line "There appears to be no open-source or affordable applications that can synthesize Verilog for these parts other than using CUPL." seems a bit confusing, as Quartus II can synthesize Verilog/VHDL for the ATF15xx series and is completely free.

but more tools are always better. so i'll check this out sometime later.
Author:  hoglet [ Mon May 15, 2023 7:56 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
Proxy wrote:
on the github, the line "There appears to be no open-source or affordable applications that can synthesize Verilog for these parts other than using CUPL." seems a bit confusing, as Quartus II can synthesize Verilog/VHDL for the ATF15xx series and is completely free.

It can, but there are a couple of caveats:
1. POF2JED seems unreliable, at least for me. It works for some designs but not for others. I think this is related to how many clocks your device uses. But I don't have definitive proof of this.
2. Certain Atmel specific feaures, such as a third global clock, cannot be used.

Dave
Author:  plasmo [ Mon May 15, 2023 12:36 pm ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
Glad to see a different design path to ATF150X. I also have had intermittent problems translating EPM7xxx to ATF150x using POF2JED, especially from EPM7064 to ATF1504. For CPLD I tend to design in schematic instead of verilog to maximize resource utilization so EDIF to CUPL translation is more useful for me.
Bill
Author:  pjdennis [ Mon May 15, 2023 4:50 pm ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
mike9repeating wrote:
[...] I've come up with a handy way to generate WinCUPL from Verilog using Yosys and a simple utility I wrote called JsonToCupl.
hoglet wrote:
Coincidenally, I also had a go at this a few months ago
Mike, Dave,

What hardware and software are you using to program the ATF15XX devices? I'm using minipro with a TL866 II programmer to program ATF22V10XX's and would like to try more capable PLD chips, such as the ATF1504XX. However I don't believe the TL866 II and minipro support the ATF15XX devices.

-Phil
Author:  Proxy [ Tue May 16, 2023 2:53 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
hmm, interesting... i've personally never really had problems with POF2JED, or i just never noticed them.

plasmo wrote:
For CPLD I tend to design in schematic instead of verilog to maximize resource utilization so EDIF to CUPL translation is more useful for me.

what exactly is "schematic"? it sounds like it would be more of a graphical thing than writing in some HDL.
i tend to just use Digital (a logic simulator) to design and test all my CPLD circuits and then simply export them to Verilog, as i like the more graphical interface and ability to directly test my circuits.
so if there is some alternative to that that works as well or better i'd be interested to hear about it.
Author:  plasmo [ Tue May 16, 2023 5:43 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
In Quartus you can enter designs as schematics of logic gates, flip flops, even TTL library components. It is graphical design entry instead of HDL text. It is a lower level design where each macrocell is accounted for. This is my CRC65 (6502 SBC) CPLD design in schematics. https://www.retrobrewcomputers.org/lib/ ... ematic.pdf
Bill
Author:  hoglet [ Tue May 16, 2023 7:41 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
pjdennis wrote:
What hardware and software are you using to program the ATF15XX devices?

I haven't got as far as programming them yet, as I keep getting distracted by other projects.

I'll certainly try to avoid buying the official ATDH1150USB programmer, as these are close to £100 in the UK. Instead, I was going to try using the ATMISP software to generate a SVF file. Then try to program this using a cheap USB blaster clone (which I already have) and open source software like OpenOCD or urJTAG. Others have had success with this route. Searching this forum for urjtag or openocd gives a few other data points that it is possible.

Also, it seems the ATMISP software supports the ByteBlaster and ByteBlasterMV parallel port programmers, which people have been able to re-create quite easily. See this link for more details. So if you have an old PC available with a parallel port, this might be an option. Altera gives the schematic for the ByteBlasterMV in the datasheet. It uses one IC: a 74HC244.

Dave
Author:  Proxy [ Tue May 16, 2023 8:26 am ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
I bought the official ATDH1150USB programmer years ago.
On one hand it was expensive (+50 EUR at the time).
but on the other hand, I use a lot of CPLDs in my designs and have to program them quite often.
So I don't really regret buying it.

Of the deciding factors are different for each person
Author:  plasmo [ Tue May 16, 2023 2:06 pm ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
I also have purchased an ATDF1150USB and ported several Altera designs to Atmel using POF2JED, or tried to—EPM7128 designs ported OK, but EPM7064 designs were complete failure except very simple test cases. I was not happy with ATF150x excess power consumption, either. I eventually abandon Atmel CPLD and bought enough EPM7xxx to last my lifetime.

Bill

PS, lots of EPM7xxx on eBay are JTAG-locked, but I took advantage of eBay return policy and keep buy-and-return until I found vendors with unlocked EPM7xxx.
Author:  Windfall [ Tue May 16, 2023 6:47 pm ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
plasmo wrote:
In Quartus you can enter designs as schematics of logic gates, flip flops, even TTL library components. It is graphical design entry instead of HDL text. It is a lower level design where each macrocell is accounted for.

Schematic entry is not lower level design. Your primitives in schematic entry are just HDL coded modules, under the hood. So, very much like using HDL, schematic entry will not dictate how the compiler and optimizer are eventually going to implement your logic. Schematic design is mainly available to allow those who don't (yet) know HDL to make simple designs, or to allow porting an existing knitwork of standard logic chips without having to rethink it in HDL. If anything, schematic entry is a higher level way to design (and a rather bad choice for complex or growing designs).
Author:  Windfall [ Tue May 16, 2023 7:02 pm ]
Post subject:  Re: Verilog to WinCUPL generator\workflow
plasmo wrote:
PS, lots of EPM7xxx on eBay are JTAG-locked, but I took advantage of eBay return policy and keep buy-and-return until I found vendors with unlocked EPM7xxx.

In addition, a lot of EPM 'S' on Ebay are not actually 'S'. I once bought a batch of 200 EPM7032STC44 on Ebay, which (eventually) turned out to be remarked EPM7032TC44, but fortunately I found someone who could program them (which requires one of Altera's old, dedicated programmers).
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