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WinCUPL - pulling a pinnode to ground or VCC
http://forum.6502.org/viewtopic.php?f=10&t=7454		 Page 1 of 1
Author:  banedon [ Thu Jan 05, 2023 11:33 am ]
Post subject:  WinCUPL - pulling a pinnode to ground or VCC
Hi guys

I suspect that this isn't possible with WinCUPL, but does anyone know if there's a way of set a pinnode to a specific value (1 or 0) without connecting it to an external pin? I.e. internally connect a pin to GND or VCC? I'm trying the have an addressable (by the MPU) eight bit latch held within an ATF1508AS with bit fields 0,1,2 set by external signals. That's fine and easy to do. However, I want bits 7,6,5,4,3 held low, so when the latch is read, there is no need to use AND #%00000111 (this assumes that if they are not set, then they will float).
I could set up an I/O pin for called 'low' and connect it (via a pull down resistor) to ground, but I'd rather not use a pin for this if I can help it.
Another way to do it is set each unused element to MPU's RESB, as when the latch is read, RESB is high, so it will means it will be inverted to low.
Something like:

Code:
/* MPU data bus and address bus assignments & decoding not shown here to keep things simple */

/* pin definitions */
Pin  1 = RESB;
Pin = detect_PCIA;      /* detection line for PCI slot A. =1 detected, =0 not detected */
Pin = detect_PCIB;      /* detection line for PCI slot B. =1 detected, =0 not detected */
Pin = detect_PCIC;      /* detection line for PCI slot C. =1 detected, =0 not detected */
pinnode = latchSelC;    /* latch C selected flag */

/* latch input assignments */
reglatchC0.L = detect_PCIA;
reglatchC1.L = detect_PCIB;
reglatchC2.L = detect_PCIC;
reglatchC3.L = !RESB;
reglatchC4.L = !RESB;
reglatchC5.L = !RESB;
reglatchC6.L = !RESB;
reglatchC7.L = !RESB;

/* always latch inputs while RESB is high */
[reglatchC7..0].LE = RESB;

/* only output to MPU data bus if the latch address is selected by the MPU address bus. This is more complicated due to the other registers, but I've made it simpler here (and removed output node definitions and assignments) to keep clear */
[D7..0].OE = RWB & latchSelC;


BTW I googled and checked the WinCUPL 'manual' that I have and, so far, can't see a way to do this. If I've missed something stupidly obvious then please poke fun gently :D.
Author:  kernelthread [ Thu Jan 05, 2023 11:54 am ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
If you only need a 3 bit latch, I would suggest you only implement a 3 bit latch. Then when you read the address which should return the latch value, return 0 for any bits which aren't implemented. For example:

[D7..0].oe = RWB & PHI2 & PLD_REG_SELECT;
D0 = (LATCH_READ_ADDR & reglatch0.Q)
# (OTHER_READ_ADDR & otherreg0.Q)
;
D1 = (LATCH_READ_ADDR & reglatch1.Q)
# (OTHER_READ_ADDR & otherreg1.Q)
;
D2 = (LATCH_READ_ADDR & reglatch2.Q)
# (OTHER_READ_ADDR & otherreg2.Q)
;
D3 = (OTHER_READ_ADDR & otherreg3.Q)
;
D4 = (OTHER_READ_ADDR & otherreg4.Q)
;
D5 = (OTHER_READ_ADDR & otherreg5.Q)
;
D6 = (OTHER_READ_ADDR & otherreg6.Q)
;
D7 = (OTHER_READ_ADDR & otherreg7.Q)
;

In this example, if you read LATCH_ADDR you get the 3 latch bits on D0-2 and the rest 0. If you read OTHER_READ_ADDR you get the full 8 bits of otherreg.
Also, if you don't have anything which needs the full 8 bits of the data bus, I would suggest only connecting the bits you need. My experience is that having lots of bus bits (either data or address) running around your design eats through logic resources remarkably quickly and routing is often more of a constraint than total number of macrocells.
Author:  banedon [ Thu Jan 05, 2023 1:02 pm ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
The project (so far) is set up for 4 x 8 bit latches, which do simulate fine with all of the other logic present - so resource-wise, things look ok, although you do make a good point.
I will be reducing the latches down, so that I have one (8 bit) latch which covers flags used for ram bank paging options and shadowing ROM. Another is for PCI slot/card (so far) detection, and finally there's one for latching the bank number for paging purposes. If nothing else comes up, I'll probably drop the last unused latch from the design.

Looking at what you've shown, that should work and will, as you say, save space. Another solution is to simply output the signals to pinnodes and then to D0, D1, D2 and skip the latch entirely - which may be a better idea. The intermediate pinnode would be so that I can control OE to D0-7.
I'm still curious if there is a facility to tie a node to ground or vcc, but my suspicion is not, given that there's a there's probably no protection if bus contention occurs and it sinks vcc from an external source through it to ground. I'll check the data sheet for the ATF1508AS latter to see if that's true.
Author:  plasmo [ Thu Jan 05, 2023 1:24 pm ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
I'm unfamiliar with WinCUPL tool, but I do know ATF1508 can have output tied to VCC or GND because this is what I do for reserved output pins. I use Quartus tool which has 'VCC' and 'GND' primitives. It seems to me "VCC" and "GND" must existed in some form so to tie the internal flipflop's reset and preset inputs to inactive state
Bill
Author:  BigDumbDinosaur [ Thu Jan 05, 2023 4:37 pm ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
banedon wrote:
I suspect that this isn't possible with WinCUPL, but does anyone know if there's a way of set a pinnode to a specific value (1 or 0) without connecting it to an external pin?

You could, but as kernelthread suggests, define the latch size to the number of bits actually needed and present 0 or 1 on unused bits in output statements.
Author:  Martin A [ Thu Jan 05, 2023 7:16 pm ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
you can always try soemthing like:
Code:
pinx =
   signal
# !signal
;


Which should set pinx high.
Author:  hoglet [ Thu Jan 05, 2023 9:06 pm ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
I think in CUPL you can just assign a pin or node to 'b'0 or 'b'1

(I've probably misunderstood the question....)

Dave
Author:  banedon [ Sat Jan 07, 2023 12:33 am ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
hoglet wrote:
I think in CUPL you can just assign a pin or node to 'b'0 or 'b'1

(I've probably misunderstood the question....)

Dave


That worked.
I have tried something line:
Code:
pinnode = tst;
tst = 1;

which failed.

However, the following works:
Code:
pinnode = tst;
tst ='b'1;

which makes sense perfect sense. Cheers! :)
Author:  BigDumbDinosaur [ Sat Jan 07, 2023 4:50 pm ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
banedon wrote:
hoglet wrote:
I think in CUPL you can just assign a pin or node to 'b'0 or 'b'1

That worked.
I have tried something line:
Code:
pinnode = tst;
tst = 1;

which failed.

However, the following works:
Code:
pinnode = tst;
tst ='b'1;

which makes sense perfect sense. Cheers! :)

Once again, unless a pinnode is needed elsewhere in your code, I recommend you do not define it and statically set it to false or true. In an output equation, you can set currently-unneeded bits to zero or one in the same fashion without consuming buried logic to do nothing.

Incidentally, the reason tst = 1 fails is because the value 1 is internally represented as a 32-bit quantity. A pin node is only able to store a single bit. Hence the need for the tst = 'b'1 syntax.

BTW, do you have the attached?

Attachment:
File comment: CUPL Programmer’s Reference
cupl_reference.pdf [814.53 KiB]
Downloaded 73 times
Author:  banedon [ Sun Jan 08, 2023 3:53 pm ]
Post subject:  Re: WinCUPL - pulling a pinnode to ground or VCC
I've now ditched the latch associated with register C and instead defined a node array which the PCI slot detection signals are fed into.
Those are then treated in the same way as the latch outs are for registers A & B.
I did try and avoid defining all 8 bits of the node array, but got array size mismatch errors when dealing with D0 to 7.

The following simulates fine (see below).

@BDD Yeah, as soon as I saw the example that hoglet posted I understood, although I assumed it'd be 8 bits, but 32 makes sense as well.
It should have occurred to me straight away.
With regards the document: I don't think I have that, as I now see where everyone gets their pin definition structure from. I'll have a good read.


Code:
/* ~~~ Inputs ~~~ */

Pin  2 = PHI2;      /* Fixed pin 2:  Main CPU clock (GCLK2). Is subject to WSE */
Pin 81 = RWB;         /* Fixed pin 12: CPU read/!write        */

Pin = detect_PCIA;      /* detection line for PCI slot A. =1 detected, =0 not detected */
Pin = detect_PCIB;      /* detection line for PCI slot B. =1 detected, =0 not detected */
Pin = detect_PCIC;      /* detection line for PCI slot C. =1 detected, =0 not detected */


/* ~~~ Outputs ~~~ */

.
.
.

/* ~~~ Input/Outputs ~~~ */

Pin = [D7..0];      /* 6502s' databus D0 to D7 */


/* ~~~ Buried Logic ~~~ */

.
.
.

pinnode = banksel;            /* bank select flag      */
pinnode = regSelA;            /* latch A selected flag */
pinnode = regSelB;            /* latch B selected flag */
pinnode = regSelC;            /* latch C selected flag */

pinnode = [banklatch7..0];         /* latch outputs to A19,18,17,16 mapped to B3..0 (top 4 bits are unused) */
pinnode = [reglatchA7..0];         /* register latch A      */
pinnode = [reglatchB7..0];         /* register latch B      */
pinnode = [regnodeC7..0];         /* reg C, array which holds the nodes */


/* ~~~~~~~~~~~~~~~~ Logic ~~~~~~~~~~~~~~~~ */


/* ~~~ Registers (latches) ~~~ */

[banklatch7..0].L = [D7..0];   /* Feed D7 to D0 into the latch */
[banklatch7..0].LE = PHI2
                   & !RWB
                   & banksel;    /* Only latch D7 to 0 if RWB=low (write mode), PHI2=high, latch is selected */

[reglatchA7..0].L = [D7..0];
[reglatchA7..0].LE = PHI2
                   & !RWB
                   & regSelA;

[reglatchB7..0].L = [D7..0];
[reglatchB7..0].LE = PHI2
                   & !RWB
                   & regSelB;

regnodeC0 = detect_PCIA;            /* feed the PCI slot detection lines into the regnode array */
regnodeC1 = detect_PCIB;
regnodeC2 = detect_PCIC;
regnodeC3 = 'b'0;
regnodeC4 = 'b'0;
regnodeC5 = 'b'0;
regnodeC6 = 'b'0;
regnodeC7 = 'b'0;

[D7..0].OE = RWB & (regSelA # regSelB # regSelC # banksel);
/* only allow D7 to D0 to output if RWB=high (read mode) and any one of the latch selects is enabled */

[D7..0] = ([reglatchA7..0] & regSelA)
    # ([reglatchB7..0] & regSelB)
    # ([regnodeC7..0] & regSelC)
    # ([banklatch7..0] & banksel);
/* All latches/registers outputs are ANDed with the respective register select.
This means that unselected registers will output all low's, while the active one will output what is stored.
The bit field outputs from all registers bits 0 to 7 are then OR'd (for that field) and fed into the respective D0 to D7 outputs.
D0 to D7 output-enables are then controlled as above. */
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