/* MPU data bus and address bus assignments & decoding not shown here to keep things simple */

/* pin definitions */
Pin  1 = RESB;
Pin = detect_PCIA;      /* detection line for PCI slot A. =1 detected, =0 not detected */
Pin = detect_PCIB;      /* detection line for PCI slot B. =1 detected, =0 not detected */
Pin = detect_PCIC;      /* detection line for PCI slot C. =1 detected, =0 not detected */
pinnode = latchSelC;    /* latch C selected flag */

/* latch input assignments */
reglatchC0.L = detect_PCIA;
reglatchC1.L = detect_PCIB;
reglatchC2.L = detect_PCIC;
reglatchC3.L = !RESB;
reglatchC4.L = !RESB;
reglatchC5.L = !RESB;
reglatchC6.L = !RESB;
reglatchC7.L = !RESB;

/* always latch inputs while RESB is high */
[reglatchC7..0].LE = RESB;

/* only output to MPU data bus if the latch address is selected by the MPU address bus. This is more complicated due to the other registers, but I've made it simpler here (and removed output node definitions and assignments) to keep clear */
[D7..0].OE = RWB & latchSelC;

pinx =
   signal
# !signal
;

pinnode = tst;
tst = 1;

pinnode = tst;
tst ='b'1;

/* ~~~ Inputs ~~~ */

Pin  2 = PHI2;      /* Fixed pin 2:  Main CPU clock (GCLK2). Is subject to WSE */
Pin 81 = RWB;         /* Fixed pin 12: CPU read/!write        */

Pin = detect_PCIA;      /* detection line for PCI slot A. =1 detected, =0 not detected */
Pin = detect_PCIB;      /* detection line for PCI slot B. =1 detected, =0 not detected */
Pin = detect_PCIC;      /* detection line for PCI slot C. =1 detected, =0 not detected */


/* ~~~ Outputs ~~~ */

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.
.

/* ~~~ Input/Outputs ~~~ */

Pin = [D7..0];      /* 6502s' databus D0 to D7 */


/* ~~~ Buried Logic ~~~ */

.
.
.

pinnode = banksel;            /* bank select flag      */
pinnode = regSelA;            /* latch A selected flag */
pinnode = regSelB;            /* latch B selected flag */
pinnode = regSelC;            /* latch C selected flag */

pinnode = [banklatch7..0];         /* latch outputs to A19,18,17,16 mapped to B3..0 (top 4 bits are unused) */
pinnode = [reglatchA7..0];         /* register latch A      */
pinnode = [reglatchB7..0];         /* register latch B      */
pinnode = [regnodeC7..0];         /* reg C, array which holds the nodes */


/* ~~~~~~~~~~~~~~~~ Logic ~~~~~~~~~~~~~~~~ */


/* ~~~ Registers (latches) ~~~ */

[banklatch7..0].L = [D7..0];   /* Feed D7 to D0 into the latch */
[banklatch7..0].LE = PHI2
                   & !RWB
                   & banksel;    /* Only latch D7 to 0 if RWB=low (write mode), PHI2=high, latch is selected */

[reglatchA7..0].L = [D7..0];
[reglatchA7..0].LE = PHI2
                   & !RWB
                   & regSelA;

[reglatchB7..0].L = [D7..0];
[reglatchB7..0].LE = PHI2
                   & !RWB
                   & regSelB;

regnodeC0 = detect_PCIA;            /* feed the PCI slot detection lines into the regnode array */
regnodeC1 = detect_PCIB;
regnodeC2 = detect_PCIC;
regnodeC3 = 'b'0;
regnodeC4 = 'b'0;
regnodeC5 = 'b'0;
regnodeC6 = 'b'0;
regnodeC7 = 'b'0;

[D7..0].OE = RWB & (regSelA # regSelB # regSelC # banksel);
/* only allow D7 to D0 to output if RWB=high (read mode) and any one of the latch selects is enabled */

[D7..0] = ([reglatchA7..0] & regSelA)
    # ([reglatchB7..0] & regSelB)
    # ([regnodeC7..0] & regSelC)
    # ([banklatch7..0] & banksel);
/* All latches/registers outputs are ANDed with the respective register select.
This means that unselected registers will output all low's, while the active one will output what is stored.
The bit field outputs from all registers bits 0 to 7 are then OR'd (for that field) and fed into the respective D0 to D7 outputs.
D0 to D7 output-enables are then controlled as above. */