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PostPosted: Mon May 16, 2022 3:02 pm 
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BigDumbDinosaur wrote:
If you have to monkey with minimization settings just to get the design to fit you are on the ragged edge with the GAL.

Good to know.

BigDumbDinosaur wrote:
You are wasting GAL resources on unnecessary functions. There is no need whatsoever to use the GAL to handle a couple of IRQs.

Yes, but if they are there for the taking, why not use them?

BigDumbDinosaur wrote:
Another consideration is the GAL’s outputs when high will be at TTL levels, not CMOS. That is not high enough to make it unambiguous to the 816 that IRQ is quiescent. Can you say “spurious interrupts?”

Yeah, I had noticed the PLD was only outputting 4V high. I'm not super happy about it. I'll keep an eye on it, but at this point I'm liking the flexibility I gained quite a bit.

BigDumbDinosaur wrote:
Using the GAL to generate an out-of-phase clock is not a good idea. As I said in an earlier post, CLKB will be skewed relative to Ø2 by as much as the GAL's tPD. Additionally, CLKB’s high phase will be at TTL levels, not CMOS. I suggest you use a flop in your clock generator to produce Ø1 and Ø2 to get rid of the skew, as well as produce a CMOS level high phase.

Yes, I got some flip/flops to test this idea. Haven't got to it yet though. But using it will likely impact the features I can include in my design. Originally, I was using a 65C02 with a single chip address decoder and two VIAs, two ACIAs, a 3-input AND for the IRQs, and two other chips for USB serial and keyboard interface. This fit nicely on a 100x100 mm PCB. Moving to the 65816, I add at least two chips for the bank address latch and data bus buffer, and likely a larger SRAM. But I had no space on the PCB, see attached image. Something has to give. Right now I don't know what it will be.

BigDumbDinosaur wrote:
You are stubbornly :D insisting on using negative logic in your output equations. That is costing you in PTs and is likely part of the reason why you are having to use QM minimization to get the design to fit.

I wouldn't say I'm stubbornly insisting on using negative logic, but I do admit struggling with the alternative. But I'm always up for a challenge. I compiled a positive logic version of my code and according to the WINCUPL DOC file it uses the exact same number of product term as the negative logic. I suppose there is more to it than that. If not then perhaps WINCUPL has been able to optimize my code in some way. I've attached the PLD (as txt files) and DOC files for anyone that's interested.

As for the use of minimization, does its use result in some inferior result? If not, I'm back where I was, why not use what's available, realizing of course, as you point out, that I'm on the ragged edge.


Attachments:
pos_logic.txt [942 Bytes]
Downloaded 59 times
neg_logic.txt [931 Bytes]
Downloaded 60 times
pos_logic.doc [9.21 KiB]
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neg_logic.doc [9.21 KiB]
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File comment: 65C02 SBC
6502_sbc-1-768x755.png
6502_sbc-1-768x755.png [ 226.93 KiB | Viewed 24942 times ]
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PostPosted: Mon May 16, 2022 4:00 pm 
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I’m late to the discussion. I’ll pleased to hear that GAL can drive output to 4V, that’s definitely CMOS level.

CPLD can certainly reduce your board size to 100mmX100mm, so can PLCC packages for 65816, 6551, and 6522.
Bill


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PostPosted: Mon May 16, 2022 4:23 pm 
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plasmo wrote:
CPLD can certainly reduce your board size to 100mmX100mm, so can PLCC packages for 65816, 6551, and 6522.

A good idea that I've eyed before but since I'm already a poster child for BigEd's So many ways for projects to go wrong post, I think I might save this one for another build.


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PostPosted: Mon May 16, 2022 6:04 pm 
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tmr4 wrote:
Yes, I got some flip/flops to test this idea. Haven't got to it yet though. But using it will likely impact the features I can include in my design...

What plasmo said. The PLCC version of the 65C816 uses about 60 percent of the space used by the DIP version. Furthermore, the PLCC version has two VCC and three Gnd connections, features that will improve system stability and freedom from ground bounce.

All WDC devices are available in PLCC. If you use PLCC you’ll gain some breathing space on your PCB. Also, you might want to take a look at SOIC packages for other discrete parts. SOIC can be manually soldered and takes about half the space of the same part in DIP. That 100 × 100 PCB has a lot more room than you think. You can cram quite a bit of hardware into 15+ square inches. Ask Garth about it. :D

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PostPosted: Mon May 16, 2022 6:32 pm 
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plasmo wrote:
I’ll pleased to hear that GAL can drive output to 4V, that’s definitely CMOS level.

However, you can't rely on that behavior because it is technically out-of-spec for the 22V10.

The guaranteed VOH for Microchip’s SPLD products is 2.4 volts with IOH at 4 mils. The theoretical maximum for VOH is 3.4 volts, but that is only achievable with very light loading. While a CMOS device draws virtually no input current when quiescent, that is not the case as its input changes state. Plus the GAL has to charge parasitic capacitance on a low-to-high transition, which constitutes additional loading. Therefore, a conservative designer would assume VOH will only meet the manufacturer’s minimum.

Of course, in a hobby unit in which property, life and limb won’t be in peril if something goes kaput there is no harm in operating outside of published specs—other than accidentally letting out the magic smoke. :D

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PostPosted: Mon May 16, 2022 6:35 pm 
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BigDumbDinosaur wrote:
What plasmo said. The PLCC version of the 65C816 uses about 60 percent of the space used by the DIP version...

Ok, maybe I'll bite. BigEd can print up a "Failure to Proceed" poster with my picture on it.

I'll have some research to do though. I bought a PLCC socket sometime ago just for the fun of it, but I don't see how I could possibly solder it to a PCB.


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PostPosted: Mon May 16, 2022 6:57 pm 
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Hee hee. It would be a less wonderful world, I think, if there were only one acceptable design. So I advise considering carefully what the tradeoffs are, and what your own priorities are.

It can be particularly difficult to navigate exactly what datasheets say, and what they don't say, and to figure out how strictly to take them: knowing, as we do, that we're probably not operating with worst-case parts in worst-case conditions with high stakes. As BDD notes, our employment, or people's lives, generally do not depend on our hobby constructions. The tradeoffs are mainly about the risk of difficult debugging or unreliable operation. (If unreliable means it crashes within seconds, that's probably a problem. But if it crashes every few weeks of runtime, well, in many cases we might never notice.)


Last edited by BigEd on Mon May 16, 2022 7:21 pm, edited 1 time in total.

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PostPosted: Mon May 16, 2022 7:00 pm 
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BigDumbDinosaur wrote:
Of course, in a hobby unit in which property, life and limb won’t be in peril if something goes kaput there is no harm in operating outside of published specs—other than accidentally letting out the magic smoke. :D

Yeah, I guess you can say I'm building to typical vs minimums. I've been blasted by some elsewhere for a design that's not technically to spec, but I'm not doing product design here or creating how-to videos. This is more about the journey for me. I want to know the technical considerations, but I'm ok with typical or actual specs, if the chips work for what I'm doing.

I know a lot of folks here are doing serious development, but for me, when (if ever) I'm done I'll likely move on to something entirely different and never pick the thing up again. After all, the smart display and PS/2 controller I'm using are in many ways significantly more powerful than either the 65C02 or 65C816. And there are much better hobby alternatives if all I cared about was processing power or getting things done.


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PostPosted: Mon May 16, 2022 8:36 pm 
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BigEd wrote:
Hee hee. It would be a less wonderful world, I think, if there were only one acceptable design. So I advise considering carefully what the tradeoffs are, and what your own priorities are.

One thing about going to PLCCs is that my build edges even closer to being a W65C816SXB development board clone, which is kind of in the opposite direction of your comment. But such a shift does open the door to, why not surface mount everything else on the board and then, why not have the PCB fabricator populate everything as well. Maybe not a bad idea. I've done plenty of soldering in my life and don't really need to focus on that part of the experience.

BigEd wrote:
The tradeoffs are mainly about the risk of difficult debugging

While frustrating, I probably get the most enjoyment from tracking down such bugs. And while I'm pleased when things work on the first try, I kind of miss that I didn't have an opportunity to troubleshoot something.


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PostPosted: Mon May 16, 2022 8:45 pm 
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tmr4 wrote:
BigDumbDinosaur wrote:
What plasmo said. The PLCC version of the 65C816 uses about 60 percent of the space used by the DIP version...

Ok, maybe I'll bite. BigEd can print up a "Failure to Proceed" poster with my picture on it.

Or, maybe you’ll luck out and it will fly on the first try. If a goal is cost-containment then it’s patent using the smallest parts you can comfortably handle will result in a smaller PCB, which will cost less to make. I went the PLCC route for that reason, as well as the possibility of shorter circuit paths that tend to favor higher clock speeds.

Quote:
I bought a PLCC socket sometime ago just for the fun of it, but I don't see how I could possibly solder it to a PCB.

Huh? PLCC sockets, at least the kinds I've used, have their pins on a 0.100 × 0.100 grid. I can readily solder one, and I’m nearly blind in the left eye.

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PostPosted: Mon May 16, 2022 9:26 pm 
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BigDumbDinosaur wrote:
If a goal is cost-containment then it’s patent using the smallest parts you can comfortably handle will result in a smaller PCB, which will cost less to make. I went the PLCC route for that reason, as well as the possibility of shorter circuit paths that tend to favor higher clock speeds.

My original goal was to build something similar to the attached image. Things morphed after I discovered that the keypad was too limiting. But I've always kept to a handheld design and thus small PCB.

BigDumbDinosaur wrote:
Huh? PLCC sockets, at least the kinds I've used, have their pins on a 0.100 × 0.100 grid. I can readily solder one, and I’m nearly blind in the left eye.

Ok, just googled, I suppose you're referring to a through hole socket. I didn't see those before. I bought a surface mount socket. Or are you saying that you solder those? If so, more power to you. I couldn't do it without melting the socket.


Attachments:
File comment: MOnSter 6502 handheld interface – by Monster6502.com
io1a.png
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PostPosted: Mon May 16, 2022 9:59 pm 
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There are even wire-wrap PLCC sockets, although they're becoming awfully hard to find.
Attachment:
WW_PLCC_44.jpg
WW_PLCC_44.jpg [ 13.3 KiB | Viewed 24902 times ]

Attachment:
WW32PLCCsocket.jpg
WW32PLCCsocket.jpg [ 26.38 KiB | Viewed 24902 times ]

A display that's more compact, more capable (being dot-matrix), easier to interface (being synchronous-serial), but also more expensive than what's in your picture is the Broadcom/Avago line. See https://www.broadcom.com/products/leds- ... s-displays, and be sure to click on "Show More Results" at the bottom to keep loading more. They come in different LED colors and different numbers of characters, are top-to-bottom and end-to-end stackable (and the serial-out of one can feed the serial-in of the next one in the daisychain, and they fit in .300" DIP sockets.

Attachment:
AvagoDotMatrixLED.jpg
AvagoDotMatrixLED.jpg [ 45.55 KiB | Viewed 24902 times ]

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PostPosted: Tue May 17, 2022 1:09 am 
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GARTHWILSON wrote:
A display that's more compact, more capable ...

For my build, the segmented display went out with the keypad. After trying out several different character displays, I decided I wanted something much more capable. I went with a 4D Systems smart display (I attached an image with it towards the bottom of page 1). It's pricey and actually in many ways much more capable than the system I'm building. But the 65xx processors can spit out data faster than the display can process, so that's something.


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PostPosted: Tue May 17, 2022 3:44 pm 
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Digging more into WINCUPL, I was able to extract more information regarding whether using negative or positive logic uses more PLD resources. For the case of the ATF22V10C and address decoding in particular I think the answer is no.

I analyzed the fuse changes for each pin after activating the Fuse Plot in the DOC file (files attached for the curious). Switching from negative to positive logic for my seven output pins resulted in the following (see post 47 for the PLD files):

  • the mode fuse on four pins changed, and
  • one pair of fuses on three pins swapped from blown to not blown or visa versa.

Code:
Pin     Neg     Pos         Mode Fuse   Swapped Fuses
16      CLKB    !CLKB           x           1
17      WE      !WE                         1
18      ROM_CS  !ROM_CS         -
19      RAM_CS  !RAM_CS         -
20      OE      !OE                         1
21      IO_CS   !IO_CS          -
23      IRQ     !IRQ

LEGEND    x : Mode fuse not blown in pos, blown in neg
          - : fuse blown in pos, not blown in neg
          1 : one pair of fuses for pin swapped state

For the ATF22V10C at least, it seems each output pin has a mode fuse to indicate whether it's active high or low. It's use or not with positive or negative logic in the case above doesn't reflect the use of more or less PLD resources as it seems these can't be used for anything else.

The swapped fuses also don't reflect the use of more or less resources since in the case above a pair of fuses are swapping state.

What I found most interesting and worthy of an update here:
  • not all of the mode fuses changed,
  • the mode fuse changes weren't always in the same direction,
  • the pins with swapped fuses all had simple logic equivalencies, and,
  • CLKB was the only pin with a mode and swapped fuse change.

It seems as if WINCUPL is doing some internal optimizations (note I haven't selected any of WINCUPL's optimization options for this analysis).

Again, I've just looked at this for the ATF22V10C and basic address decoding. It's possible that the logic used here is easier for WINCUPL to optimize and these results won't hold for more complicated situations. In that case positive logic might lead to more efficient PLD usage. At the same time, I know almost nothing about all of this and my analysis could be totally wrong. So any feedback regarding it would be appreciated.


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pos_logic_fuse_plot.doc [17.97 KiB]
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neg_logic_fuse_plot.doc [17.97 KiB]
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PostPosted: Tue May 17, 2022 8:40 pm 
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tmr4 wrote:
Digging more into WINCUPL, I was able to extract more information regarding whether using negative or positive logic uses more PLD resources. For the case of the ATF22V10C and address decoding in particular I think the answer is no...

All of my experience with CUPL has been with the CPLDs, not the GALs. In playing around with positive vs, negative logic, I did see a greater use of PTs with the latter. That being the case, apparently there are some significant differences in the internal architecture of the two PLD types. As always, YMMV.

One thing I noted in examining your two .DOC files (note to the uninitiated: a .DOC file generated by CUPL compilation is not an MS Word document) is the huge amount of logic being consumed to generate EXRAM. I suspect that is the result of the idiosyncratic memory map you’ve set up. Also not helping is a GAL doesn't have buried nodes to assist with bank bits generation and the aggregation certain kinds of address bus conditions. In your application, I believe the availability of buried nodes would have significantly reduced logic consumption.

Edit: Fixed a typo.

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Last edited by BigDumbDinosaur on Wed May 18, 2022 4:34 am, edited 2 times in total.

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