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CPLD + 6502 Trainer http://forum.6502.org/viewtopic.php?f=10&t=6974	Page 5 of 6

Author:	Dr Jefyll [ Sat Aug 20, 2022 9:57 pm ]
Post subject:	Re: CPLD + 6502 Trainer
plasmo wrote: Jeff, I’m a big fan of rapid spiral development cycle because each phase of product development has a particular perspective and language for communication; sometimes innovation occurred when moving from one phase into next when perspective and language shifted. "Rapid... Spiral... Development... Cycle" ????! ( Oh-kay, then! )

Author:	Berzerkula [ Wed Aug 24, 2022 1:21 am ]
Post subject:	Re: CPLD + 6502 Trainer
plasmo wrote: The modified trainer appears to work at 25.175MHz. Adjusting the baud clock generator and testing with 29.5MHz clock, I see it'll boot and execute the monitor commands but memory diagnostic is failing intermittently so I believe the design is on the hairy edge at 29.5MHz. I'm a bit disappointed because CRC65 is able to run reliably at 29.5MHz using the same 25nS RAM. Perhaps the reason is because CRC65 is a spartan design with PC board half the size and minimal set of components where the trainer is twice as large pc board with RAM, ROM, Z80 socket, expansion connector and the 25nS RAM is on a SOJ-to-DIP carrier board. The added capacitance probably pushes it to the hairy edge at 29.5MHz. The good news is it should have good design margin at 25.175MHz. Design file for 25.175MHz is attached for people wanting to try it Bill, With the carrier board, was it a straight pin to pin adapter, or did you route the pins to match what the AS6C4008 with the CY7C109 layout (Some differences in pinout, address lines, and CE1 CE2 lines)? -William

Author:

plasmo [ Wed Aug 24, 2022 3:35 am ]

Post subject:

Re: CPLD + 6502 Trainer

I never documented the design! Hmmm, I've made several designs in that topic area (piggyback VGA); you can see an assembled stack here.

I'll fix that soon, but attached are schematic and gerber photoplots. The short answer is: yes, it is pin-to-pin connections between AS6C1008 and CY7C109. CS2 (pin 30) of CY7C109 and AS6C1008 is enabled by driving high with CPLD output.
Bill

Attachments:

RAM_bd_r0_gerber.zip [10.89 KiB]
Downloaded 78 times

RAM_BD_scm.pdf [16.59 KiB]
Downloaded 79 times

Author:	Berzerkula [ Wed Aug 24, 2022 4:49 am ]
Post subject:	Re: CPLD + 6502 Trainer
plasmo wrote: I never documented the design! Hmmm, I've made several designs in that topic area (piggyback VGA); you can see an assembled stack here. I'll fix that soon, but attached are schematic and gerber photoplots. The short answer is: yes, it is pin-to-pin connections between AS6C1008 and CY7C109. CS2 (pin 30) of CY7C109 and AS6C1008 is enabled by driving high with CPLD output. Bill Thank you for sharing that with us in this forum. I've been getting used to using KiCad after using Eagle for decades, and designed a 32-SOJ (400mil) to DIP32 (600mil) adapter. The dimensions are very tight, and also included the options for a bypass cap when VSS is at pin 16 and VDD is at pin 32. Could be used for anything, but targeting SRAM (CY7C109B-15VC). Looking forward to getting VGA going. I have plenty of spare VGA jacks to get a bit further. A lot going on, hope to get back to the sessions as they are available. -William

Author:	Berzerkula [ Tue Sep 06, 2022 9:28 pm ]
Post subject:	Re: CPLD + 6502 Trainer
plasmo wrote: The short answer is: yes, it is pin-to-pin connections between AS6C1008 and CY7C109. CS2 (pin 30) of CY7C109 and AS6C1008 is enabled by driving high with CPLD output. Bill Hello Bill, I was wondering if it was a pin to pin connection because the surface mount part pinouts differ from the DIP parts. VCC and VSS are on different pins among other signals. Or am I missing something? I'm looking at these datasheets: AS6C1008 https://www.alliancememory.com/wp-content/uploads/pdf/AS6C1008feb2007.pdf CY7C109 and CY7C109B https://www.teledynedefenseelectronics. ... 9_1009.pdf https://media.digikey.com/pdf/Data%20Sh ... C1009B.pdf - William

Author:	plasmo [ Wed Sep 07, 2022 12:30 am ]
Post subject:	Re: CPLD + 6502 Trainer
Looking at the datasheets, pin assignments of DIP AS6C1008 are the same as pin assignments of SOJ CY7C109. Pin 1 is NC, pins 13-15, pins 17-21 are data, chip enable active low is 22, chip enable active high is 30, output enable is 24 and write enable is 29. VCC is 32 and GND is 16. I don't see any differences? Bill

Author:

Berzerkula [ Wed Sep 07, 2022 8:32 am ]

Post subject:

Re: CPLD + 6502 Trainer

plasmo wrote:

Looking at the datasheets, pin assignments of DIP AS6C1008 are the same as pin assignments of SOJ CY7C109. Pin 1 is NC, pins 13-15, pins 17-21 are data, chip enable active low is 22, chip enable active high is 30, output enable is 24 and write enable is 29. VCC is 32 and GND is 16. I don't see any differences?
Bill

Greetings,

What I was meaning is that if we put a surface mount device on an adapter and have a straight through pinout, it is going to be an interesting outcome.

DIP pinouts between them are okay. The surface mount pinouts differ between DIP and SOJ32 or SOI or others.

The VCC and VSS pins change, along with the signals. How is it the adapter you made straight pin for pin works and not blowing up the SMD IC's?

The datasheet states for the .... oh crud, now I see it, the SOJ has the same pinout, it's the TSOP which has a different layout... no matter. Now I see it! Doh!

Your comment made me look again. Many times I looked at the datasheet and wondered then poof! Just cause a picture looks like a DIP or PDIP or some other, SOJ may be there, too.
Received the PCB's today. I think they will work well. I've only aligned the device by rolling my fingers, it's not soldered. Making sure it all is aligned. I think it will be a good device around my lab.

- William

Attachments:

SOJ32_DIP32.jpg [ 1.57 MiB | Viewed 14127 times ]

Author:

bill8n95 [ Tue Sep 19, 2023 8:54 pm ]

Post subject:

Re: CPLD + 6502 Trainer

Thanks Bill for this great design. That inspired me to draw a slightly different layout. I like to see it more like an Z80 (and 6502 / 6809) SBC rather than a CPLD trainer, so with this in mind, I made this (based on your work).
Gerber files included.

Attachments:

Z80_SBC.rar [134.71 KiB]
Downloaded 35 times

PCB_image.png [ 462.57 KiB | Viewed 13128 times ]

Author:

bill8n95 [ Tue Sep 19, 2023 9:58 pm ]

Post subject:

Re: CPLD + 6502 Trainer

The schematics are here. I tried to make as little as possible changes to v1.

Changes from your v1 are:
1) 28-pin (32 KB) and 32-pin (512 KB) ICs are supported for both RAM and Program Memory (PROM, UV EPROM and Flash memory). The 28-pin EEPROM is not supported (where, pin 1 = A14 , and pin 27 = /WE)
2) JP2 connects /OERAM to /CSRAM (pins 1-2 jumpered) for compatibility with your v1, or (pins 2-3 jumpered) /OERAM is controlled by T29 (CPLD pin 52) [also T29 is accessed through this JP2 pin3 = T29 pin]
3) Only for 28-pin Program memory: if Flash memory is used then JP3 connects /WEPROM to CPLD pin 28 (pins 1-2 jumpered) for compatibility with your v1,
or if PROM/UV-EPROM is used (pins 2-3 jumpered) now memory's pin 1 is VPP and it's connected to ground [also CPLD pin 28 is accessed through this JP3 pin 3]
4) Pins 1 and 3 of JP1 are swapped in relation to v1 (by accident)
5) Pin Header P1 is 2 rows by 17 and connects only Address pins A(15:0). Signal CLK does not reach CLK at CPU, and a jumper cable is needed if going to be used. All pins at the upper row are not connected and wires are needed if they are going to be used. (due to only 2 layer pcb)
6) JTAG pin header uses different layout (to match most of JTAG interface cables like TE0300 or Digilent JTAG-HS2)
7) UART (Serial) pin header uses different layout (to match DFRobot FT232RL basic breakout board)

Attachments:

Schematic_image.png [ 1.39 MiB | Viewed 13118 times ]

Author:	plasmo [ Thu Sep 21, 2023 1:57 am ]
Post subject:	Re: CPLD + 6502 Trainer
I like it, it is a nice redesign of rev1 Trainer with 6809, 6502, Z80 all hooked up. You will find many uses for your board. I have built up about 6 trainers for different applications and with different processors. I'm interested in your 6809 development since I'm not very familiar with that processor. I have a few thoughts about your design. Porting RomWBW to your trainer populated with Z80 is a logical development which means you need expansion board for either CF disk or SD disk. RomWBW's serial port needs hardware handshake, so you need to add RTS handshake to your serial connector. 6502 and 65816 have very similar pin out. You may want to look at your 6502 connections and see what need to be added or jumperable to accommodate 65816. One of design I was exploring is front panel for Z80, 6502, and 6809. You can enter address/data via PS2 keyboard and see the address/data on the 7-segment displays. The front panel capability requires bus arbitration signal to take over processor bus and also manipulate RDY/Wait to single step instruction execution. I think you'll have lots of fun with this board. Bill

Author:	bill8n95 [ Mon Sep 25, 2023 6:53 pm ]
Post subject:	Re: CPLD + 6502 Trainer
Thank you Bill, the board is already 10 x 10 cm (which is the upper limit for a low cost pcb manufactured at some pcb houses), so one solution would be to use smd 7-segment displays and smd SD card socket at the other layer, underneath the 7-seg displays. Adding RTS signal is no problem. T7 or T8 or T28 or T29 could be used for this purpose. Yes, 65816 could also be easy. Maybe, a big problem is that the pcb is just 2 layers and I think 65816 should take the place of one of 6502 / z80 / 6809. Maybe 4 processors could fit ! About that interaction of PS2 keyboard and address/data, do you have any working CPLD design files ?

Author:

Dr Jefyll [ Mon Sep 25, 2023 8:17 pm ]

Post subject:

Re: CPLD + 6502 Trainer

bill8n95 wrote:

Maybe 4 processors could fit !

Thanks for sharing your work, bill8n95 -- it's great to see what you've done with this!

Additional 65xx processors might not be that difficult, given that even the '816 has a pinout that's highly similar to the '02 and the 'C02. Perhaps you'll find the attached diagram helpful.

You'll see I've used red dots to mark cases where a pin on one CPU fails to match the function of that same pin on the sibling CPUs. And in a few cases the signal name may differ but there's no red dot; that's because the manufacturers don't always use the same terminology, even though the function of the pin is the same.

-- Jeff

Attachments:

65xx DIP pinouts '816 + 'C02 + 'C02.png [ 48.36 KiB | Viewed 12953 times ]

Author:	bill8n95 [ Tue Sep 26, 2023 9:09 am ]
Post subject:	Re: CPLD + 6502 Trainer
Yes, you are absolutely right! But... what I meant, is that my biggest concern is the pcb space, combined with the need for as little as possible via usage (for signal integrity purposes). Of cource, I know that even 10 MHz is not a problem (the frequency is too low), but... ok. I promise to design one 10x10 cm pcb with 4 processors, as soon as I find some time ! By the way, I don't consider this my work, because the initial thought and design is yours! So, you are free to even name it v1.2 and upload it even at retrobrewcomputers.org I can send you whatever related to this pcb.

Author:

bill8n95 [ Tue Sep 26, 2023 10:16 am ]

Post subject:

Re: CPLD + 6502 Trainer

Also, inspired from a video named "Single Stepping a Z80 on a Breadboard" in a youtube channel named "Kenneth Finnegan", I made this adapter for the Z80, so I can see every signal of this processor, when using the Single-step function. It uses 74HC245 buffers.

Attachments:

Z80_signals_3.jpg [ 2.55 MiB | Viewed 12920 times ]

Z80_signals_2.jpg [ 2.37 MiB | Viewed 12920 times ]

Z80_signals_1.jpg [ 2.27 MiB | Viewed 12920 times ]

Author:

bill8n95 [ Tue Sep 26, 2023 10:22 am ]

Post subject:

Re: CPLD + 6502 Trainer

Of cource, I designed some Debounce+Single-pulse logic in the CPLD, that is between the Step switch and the Clock input of the Z80. The CPLD design uses the oscillator of the pcb to measure a 20 ms delay period of no-change, and it outputs a clean single clock pulse to the Z80, for single step mode. So, the initial pcb layout should be slightly modified (hopefully with no cut-solder of the traces), by using some wires

Attachments:

Single step.jpg [ 11.99 MiB | Viewed 12920 times ]

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