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GAL16V8 Memory decoder http://forum.6502.org/viewtopic.php?f=10&t=6797 |
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Author: | anonyfous [ Thu Sep 23, 2021 3:58 pm ] |
Post subject: | GAL16V8 Memory decoder |
Hello, I am not sure if this belongs to this forum, but maybe someone could help me. I am trying to reverse engineer a memory decoder fom an old studio FX unit. It seems to be simple combinatorial logic. I am reading the input > output combinations with arduino and then I am trying to replicate those tables with WinCUPL, but I can't get it right. I am having problem with the "SYNCDT" signal. I don't know how to write the logic equations correctly. I am posting my .PLD file and the tables from the original and newly programmed chip. The problem is with last few lines 0122 - 0127, the SYNCDT signal should be LOW, but it stays HIGH and when I try to write some more equations, I get compiler error "The number of product terms needed to implement the logic expression for the given variable exceeds the capacity of the output pin for which it was declared." Any help would be super cool, thank you. A. PLD File: Code: Name Lexicon M300 MDEC 1.01 ; PartNo 00 ; Date 13.09.2021 ; Revision 01 ; Designer ; Company PLD lousk ; Assembly None ; Location ; Device g16v8; /* *************** INPUT PINS *********************/ PIN [1..7] = [ A0 ..6]; /* Upper addresses */ PIN 8=AS; /* Addres srobe */ PIN 9=DMAACK; /* DMA Acknowledge */ PIN 11=RORMP;/* ROM Re-mapping */ /* *************** OUTPUT PINS *********************/ PIN 12=!PERIPH ; /* PERIPH */ PIN 13=!DUART ; /* DUART */ PIN 14=!ZRAM2 ; /* ZRAM2 */ PIN 15=!ZRAM1 ; /* ZRAM1 */ PIN 16=!SYNCDT ; /* SYNCDT */ PIN 17=!RAM0 ; /* RAM0 */ PIN 18=!ROM1 ; /* ROM1 */ PIN 19=!ROM0 ; /* ROM0 */ /* *****************Declarations************** */ /* **************EQUATIONS************ */ ROM0 = ((!A0 & !A1 & !A2 & A3) & !AS & RORMP) # ((!A0 & !A1 & !A2 & !A3) & !AS & !RORMP); ROM1 = (!A0 & !A1 & A2) & !AS; RAM0 = (!A0 & !A1 & !A2 & !A3 & !A4) & !AS & RORMP; SYNCDT = AS # !A0 & A1 # A0 & !A1 # A0 & !A2 # A0 & !A3 # !A2 & A3 & !RORMP # A0 & !A4 & !A5 & !A6 # A0 & !A4 & A5 & !A6 # !A2 & !A3 & A4 & RORMP; ZRAM1 = !DMAACK & !AS; ZRAM2 = !DMAACK & ((A0 & A3) # (A0 & A2) # (A0 & A1)) & !AS; DUART = !AS & (A0 & A1 & A2 & A3 & !A4 & !A5 & !A6); PERIPH = !AS & (A0 & A1 & A2 & A3 & !A4 & !A5 & A6); Read from the original chip: Code: Table 2 - AS/ LOW ----------------------------- STEP RORMP DMAACK AS/ A19-A13 ROM0 ROM1 RAM0 SYNCDT ZRAM1 ZRAM2 DUART PERIPH 0000 110 0000000 H H L H H H H H 0001 110 0000001 H H L H H H H H 0002 110 0000010 H H L H H H H H 0003 110 0000011 H H L H H H H H 0004 110 0000100 H H H L H H H H 0005 110 0000101 H H H L H H H H 0006 110 0000110 H H H L H H H H 0007 110 0000111 H H H L H H H H 0008 110 0001000 L H H H H H H H 0009 110 0001001 L H H H H H H H 0010 110 0001010 L H H H H H H H 0011 110 0001011 L H H H H H H H 0012 110 0001100 L H H H H H H H 0013 110 0001101 L H H H H H H H 0014 110 0001110 L H H H H H H H 0015 110 0001111 L H H H H H H H 0016 110 0010000 H L H H H H H H 0017 110 0010001 H L H H H H H H 0018 110 0010010 H L H H H H H H 0019 110 0010011 H L H H H H H H 0020 110 0010100 H L H H H H H H 0021 110 0010101 H L H H H H H H 0022 110 0010110 H L H H H H H H 0023 110 0010111 H L H H H H H H 0024 110 0011000 H L H H H H H H 0025 110 0011001 H L H H H H H H 0026 110 0011010 H L H H H H H H 0027 110 0011011 H L H H H H H H 0028 110 0011100 H L H H H H H H 0029 110 0011101 H L H H H H H H 0030 110 0011110 H L H H H H H H 0031 110 0011111 H L H H H H H H 0032 110 0100000 H H H L H H H H 0033 110 0100001 H H H L H H H H 0034 110 0100010 H H H L H H H H 0035 110 0100011 H H H L H H H H 0036 110 0100100 H H H L H H H H 0037 110 0100101 H H H L H H H H 0038 110 0100110 H H H L H H H H 0039 110 0100111 H H H L H H H H 0040 110 0101000 H H H L H H H H 0041 110 0101001 H H H L H H H H 0042 110 0101010 H H H L H H H H 0043 110 0101011 H H H L H H H H 0044 110 0101100 H H H L H H H H 0045 110 0101101 H H H L H H H H 0046 110 0101110 H H H L H H H H 0047 110 0101111 H H H L H H H H 0048 110 0110000 H H H L H H H H 0049 110 0110001 H H H L H H H H 0050 110 0110010 H H H L H H H H 0051 110 0110011 H H H L H H H H 0052 110 0110100 H H H L H H H H 0053 110 0110101 H H H L H H H H 0054 110 0110110 H H H L H H H H 0055 110 0110111 H H H L H H H H 0056 110 0111000 H H H L H H H H 0057 110 0111001 H H H L H H H H 0058 110 0111010 H H H L H H H H 0059 110 0111011 H H H L H H H H 0060 110 0111100 H H H L H H H H 0061 110 0111101 H H H L H H H H 0062 110 0111110 H H H L H H H H 0063 110 0111111 H H H L H H H H 0064 110 1000000 H H H L H H H H 0065 110 1000001 H H H L H H H H 0066 110 1000010 H H H L H H H H 0067 110 1000011 H H H L H H H H 0068 110 1000100 H H H L H H H H 0069 110 1000101 H H H L H H H H 0070 110 1000110 H H H L H H H H 0071 110 1000111 H H H L H H H H 0072 110 1001000 H H H L H H H H 0073 110 1001001 H H H L H H H H 0074 110 1001010 H H H L H H H H 0075 110 1001011 H H H L H H H H 0076 110 1001100 H H H L H H H H 0077 110 1001101 H H H L H H H H 0078 110 1001110 H H H L H H H H 0079 110 1001111 H H H L H H H H 0080 110 1010000 H H H L H H H H 0081 110 1010001 H H H L H H H H 0082 110 1010010 H H H L H H H H 0083 110 1010011 H H H L H H H H 0084 110 1010100 H H H L H H H H 0085 110 1010101 H H H L H H H H 0086 110 1010110 H H H L H H H H 0087 110 1010111 H H H L H H H H 0088 110 1011000 H H H L H H H H 0089 110 1011001 H H H L H H H H 0090 110 1011010 H H H L H H H H 0091 110 1011011 H H H L H H H H 0092 110 1011100 H H H L H H H H 0093 110 1011101 H H H L H H H H 0094 110 1011110 H H H L H H H H 0095 110 1011111 H H H L H H H H 0096 110 1100000 H H H L H H H H 0097 110 1100001 H H H L H H H H 0098 110 1100010 H H H L H H H H 0099 110 1100011 H H H L H H H H 0100 110 1100100 H H H L H H H H 0101 110 1100101 H H H L H H H H 0102 110 1100110 H H H L H H H H 0103 110 1100111 H H H L H H H H 0104 110 1101000 H H H L H H H H 0105 110 1101001 H H H L H H H H 0106 110 1101010 H H H L H H H H 0107 110 1101011 H H H L H H H H 0108 110 1101100 H H H L H H H H 0109 110 1101101 H H H L H H H H 0110 110 1101110 H H H L H H H H 0111 110 1101111 H H H L H H H H 0112 110 1110000 H H H L H H H H 0113 110 1110001 H H H L H H H H 0114 110 1110010 H H H L H H H H 0115 110 1110011 H H H L H H H H 0116 110 1110100 H H H L H H H H 0117 110 1110101 H H H L H H H H 0118 110 1110110 H H H L H H H H 0119 110 1110111 H H H L H H H H 0120 110 1111000 H H H L H H L H 0121 110 1111001 H H H H H H H L 0122 110 1111010 H H H L H H H H 0123 110 1111011 H H H L H H H H 0124 110 1111100 H H H L H H H H 0125 110 1111101 H H H L H H H H 0126 110 1111110 H H H L H H H H 0127 110 1111111 H H H L H H H H ------------Done------------- Read from the new chip: Code: STEP RORMP DMAACK AS/ A19-A13 ROM0 ROM1 RAM0 SYNCDT ZRAM1 ZRAM2 DUART PERIPH
0000 110 0000000 H H L H H H H H 0001 110 0000001 H H L H H H H H 0002 110 0000010 H H L H H H H H 0003 110 0000011 H H L H H H H H 0004 110 0000100 H H H L H H H H 0005 110 0000101 H H H L H H H H 0006 110 0000110 H H H L H H H H 0007 110 0000111 H H H L H H H H 0008 110 0001000 L H H H H H H H 0009 110 0001001 L H H H H H H H 0010 110 0001010 L H H H H H H H 0011 110 0001011 L H H H H H H H 0012 110 0001100 L H H H H H H H 0013 110 0001101 L H H H H H H H 0014 110 0001110 L H H H H H H H 0015 110 0001111 L H H H H H H H 0016 110 0010000 H L H H H H H H 0017 110 0010001 H L H H H H H H 0018 110 0010010 H L H H H H H H 0019 110 0010011 H L H H H H H H 0020 110 0010100 H L H H H H H H 0021 110 0010101 H L H H H H H H 0022 110 0010110 H L H H H H H H 0023 110 0010111 H L H H H H H H 0024 110 0011000 H L H H H H H H 0025 110 0011001 H L H H H H H H 0026 110 0011010 H L H H H H H H 0027 110 0011011 H L H H H H H H 0028 110 0011100 H L H H H H H H 0029 110 0011101 H L H H H H H H 0030 110 0011110 H L H H H H H H 0031 110 0011111 H L H H H H H H 0032 110 0100000 H H H L H H H H 0033 110 0100001 H H H L H H H H 0034 110 0100010 H H H L H H H H 0035 110 0100011 H H H L H H H H 0036 110 0100100 H H H L H H H H 0037 110 0100101 H H H L H H H H 0038 110 0100110 H H H L H H H H 0039 110 0100111 H H H L H H H H 0040 110 0101000 H H H L H H H H 0041 110 0101001 H H H L H H H H 0042 110 0101010 H H H L H H H H 0043 110 0101011 H H H L H H H H 0044 110 0101100 H H H L H H H H 0045 110 0101101 H H H L H H H H 0046 110 0101110 H H H L H H H H 0047 110 0101111 H H H L H H H H 0048 110 0110000 H H H L H H H H 0049 110 0110001 H H H L H H H H 0050 110 0110010 H H H L H H H H 0051 110 0110011 H H H L H H H H 0052 110 0110100 H H H L H H H H 0053 110 0110101 H H H L H H H H 0054 110 0110110 H H H L H H H H 0055 110 0110111 H H H L H H H H 0056 110 0111000 H H H L H H H H 0057 110 0111001 H H H L H H H H 0058 110 0111010 H H H L H H H H 0059 110 0111011 H H H L H H H H 0060 110 0111100 H H H L H H H H 0061 110 0111101 H H H L H H H H 0062 110 0111110 H H H L H H H H 0063 110 0111111 H H H L H H H H 0064 110 1000000 H H H L H H H H 0065 110 1000001 H H H L H H H H 0066 110 1000010 H H H L H H H H 0067 110 1000011 H H H L H H H H 0068 110 1000100 H H H L H H H H 0069 110 1000101 H H H L H H H H 0070 110 1000110 H H H L H H H H 0071 110 1000111 H H H L H H H H 0072 110 1001000 H H H L H H H H 0073 110 1001001 H H H L H H H H 0074 110 1001010 H H H L H H H H 0075 110 1001011 H H H L H H H H 0076 110 1001100 H H H L H H H H 0077 110 1001101 H H H L H H H H 0078 110 1001110 H H H L H H H H 0079 110 1001111 H H H L H H H H 0080 110 1010000 H H H L H H H H 0081 110 1010001 H H H L H H H H 0082 110 1010010 H H H L H H H H 0083 110 1010011 H H H L H H H H 0084 110 1010100 H H H L H H H H 0085 110 1010101 H H H L H H H H 0086 110 1010110 H H H L H H H H 0087 110 1010111 H H H L H H H H 0088 110 1011000 H H H L H H H H 0089 110 1011001 H H H L H H H H 0090 110 1011010 H H H L H H H H 0091 110 1011011 H H H L H H H H 0092 110 1011100 H H H L H H H H 0093 110 1011101 H H H L H H H H 0094 110 1011110 H H H L H H H H 0095 110 1011111 H H H L H H H H 0096 110 1100000 H H H L H H H H 0097 110 1100001 H H H L H H H H 0098 110 1100010 H H H L H H H H 0099 110 1100011 H H H L H H H H 0100 110 1100100 H H H L H H H H 0101 110 1100101 H H H L H H H H 0102 110 1100110 H H H L H H H H 0103 110 1100111 H H H L H H H H 0104 110 1101000 H H H L H H H H 0105 110 1101001 H H H L H H H H 0106 110 1101010 H H H L H H H H 0107 110 1101011 H H H L H H H H 0108 110 1101100 H H H L H H H H 0109 110 1101101 H H H L H H H H 0110 110 1101110 H H H L H H H H 0111 110 1101111 H H H L H H H H 0112 110 1110000 H H H L H H H H 0113 110 1110001 H H H L H H H H 0114 110 1110010 H H H L H H H H 0115 110 1110011 H H H L H H H H 0116 110 1110100 H H H L H H H H 0117 110 1110101 H H H L H H H H 0118 110 1110110 H H H L H H H H 0119 110 1110111 H H H L H H H H 0120 110 1111000 H H H L H H L H 0121 110 1111001 H H H H H H H L 0122 110 1111010 H H H L H H H H 0123 110 1111011 H H H H H H H H 0124 110 1111100 H H H H H H H H 0125 110 1111101 H H H H H H H H 0126 110 1111110 H H H H H H H H 0127 110 1111111 H H H H H H H H ------------Done------------- |
Author: | gfoot [ Thu Sep 23, 2021 4:21 pm ] |
Post subject: | Re: GAL16V8 Memory decoder |
Quote: # A0 & !A4 & !A5 & !A6 # A0 & !A4 & A5 & !A6 It looks like A5 is irrelevant here so you could collapse these two into one term. Would that help? Overall though it looks like syncdt is high when address is 00000xx or 0001xxx or 001xxxx or 1111001 - that's only four product terms needed. |
Author: | anonyfous [ Thu Sep 23, 2021 5:11 pm ] |
Post subject: | Re: GAL16V8 Memory decoder |
When I collapsed those two to Code: # A0 & !A4 & !A6 the output is still the same. And yes, thats right for the table I posted, but it is a bit more complicated, because the SYNCDT is a bit different when RORMP is LOW (the whole thing is active LOW) and it is also always LOW (trough the whole table) when AS/ is HIGH (AS indicates that there is a valid address on the input). I can post the other two tables - with AS/ HIGIH and RORMP LOW if it helps. Anyway, thank you! |
Author: | BigEd [ Thu Sep 23, 2021 6:36 pm ] |
Post subject: | Re: GAL16V8 Memory decoder |
Welcome, anonyfous! It's possible - maybe even likely - that many of the entries in the recovered truth table are actually don't-cares, because they can't happen or because it makes no difference. In which case, your recovered equations are over-specified, and use more resources. But even if this is so, I can't think of an easy way to make use of it: I think perhaps you'd need to reconstruct a higher level view of what's being accomplished, and make a new design to accomplish the same. |
Author: | anonyfous [ Thu Sep 23, 2021 7:50 pm ] |
Post subject: | Re: GAL16V8 Memory decoder |
Hmm, I think you are right, because a while ago I was able to get it done, both GALs now behave the same when I put them trough the arduino scan, but when I put the newly programmed chip to the Lexicon it throws an bus error. I guess this will be harder than I thought. |
Author: | anonyfous [ Thu Sep 23, 2021 8:02 pm ] | ||
Post subject: | Re: GAL16V8 Memory decoder | ||
Anyway here are the tables that I was able to read, the AS/ signal indicates a valid address, so there are only five tables as the rest of the input combinations when the AS/ is HIGH throws the same output as shown in table 1. I am not sure that I undestand what the DMAACK signal does, because it selects (according to table 4 and 5) two memory chips at the same time which doesn't seem right to me, but I have no idea where to go next. Final PLD: Code: Name LEXICON ;
PartNo 00 ; Date 13.09.2021 ; Revision 01 ; Designer ; Company Private ; Assembly None ; Location U24; Device g16v8a; /* *************** INPUT PINS *********************/ PIN [1..7] = [ A0 ..6]; /* addresses */ PIN 8=AS; /* Addres srobe */ PIN 9=DMAACK; /* DMA Acknowledge */ PIN 11=RORMP;/* ROM Re-mapping */ /* *************** OUTPUT PINS *********************/ PIN 12=!PERIPH ; /* PERIPH */ PIN 13=!DUART ; /* DUART */ PIN 14=!ZRAM2 ; /* ZRAM2 */ PIN 15=!ZRAM1 ; /* ZRAM1 */ PIN 16=SYNCDT ; /* SYNCDT */ PIN 17=!RAM0 ; /* RAM0 */ PIN 18=!ROM1 ; /* ROM1 */ PIN 19=!ROM0 ; /* ROM0 */ /* *****************Declarations************** */ /* **************EQUATIONS************ */ ROM0 = ((!A0 & !A1 & !A2 & A3) & !AS & RORMP) # ((!A0 & !A1 & !A2 & !A3) & !AS & !RORMP); ROM1 = (!A0 & !A1 & A2) & !AS; RAM0 = (!A0 & !A1 & !A2 & !A3 & !A4) & !AS & RORMP; SYNCDT = !A0 & !A1 & !A2 & !A3 & !A4 & RORMP & !AS # !A0 & !A1 & !A2 & !A3 & !RORMP & !AS # !A0 & !A1 & !A2 & A3 & RORMP & !AS # !A0 & !A1 & A2 & !AS # A0 & A1 & A2 & A3 & !A4 & !A5 & A6 & !AS; ZRAM1 = !DMAACK & !AS & A0; ZRAM2 = !DMAACK & ((A0 & A3) # (A0 & A2) # (A0 & A1)) & !AS; DUART = !AS & (A0 & A1 & A2 & A3 & !A4 & !A5 & !A6); PERIPH = !AS & (A0 & A1 & A2 & A3 & !A4 & !A5 & A6);
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Author: | anonyfous [ Fri Sep 24, 2021 10:53 am ] |
Post subject: | Re: GAL16V8 Memory decoder |
Maybe I am onto something. When tried to count the addresses the opposite way from 1111111 to 0000000 I have found that the ZRAM outputs are different (ZRAM outs are only active (LOW) when DMAACK input is LOW). I am not sure what that means, but I have found this in the service manual. Quote: The 68008 has an asynchronous bus interface. This means that when the 68008
initiates a bus cycle, it will normally not finish the cycle until it has received acknowledgment from the addressed device (DTACK/). The Host board contains circuitry to handle a number of device-dependent cases: Most of the on-board devices are sufficiently fast to issue a DTACK/ on the first 8MHz cycle after data strobe. This creates a psuedo-synchronous cycle with 0 wait states for reads and 1 wait state for writes. Other devices, specifically the DUART (U20) and the DSP board Slave ZRAM, will take a longer and indeterminate amount of time to respond. Either case drives U35 pin 12 high and this in turn will drive U46 pin 12 low on the next edge of 8MHz. This will hold off DTACK/ until either the DUART acknowledge (DDTACK/) or the ZRAM acknowledge (DMAACK) is asserted. As mentioned above, the 68008 suspends processing during a bus cycle until DTACK/ is asserted. This means the system will hang if DTACK/ does not work as expected. The 68008 can recover from an unterminated bus cycle (DTACK/ not asserted) if a circuit is provided that drives the BERR/ input low after some time interval. The BERR/ generator is a 74HC393 (U36) wired as a divide-by-256 counter, and an inverter (U34). When AS/ is asserted at the beginning of a bus cycle, the counter begins counting 4MHz cycles. If 128 cycles are counted (32 usec) and AS/ is still asserted, pin 6 of the 393 goes high. This is inverted to generate the BERR/ signal. BERR/ causes the 68008 to begin exception processing. AS/ is released, which resets U36, clearing the BERR/ signal. In a normal cycle, AS/ is de-asserted in less than 32 usec and the counter is reset before BERR/ is asserted. |
Author: | obsoletemachines [ Thu Dec 08, 2022 5:15 pm ] |
Post subject: | Re: GAL16V8 Memory decoder |
hi, this is interesting. What lexicon unit is this for? I'm thinking of reading some GALs on my Quantec QRS/XL effects unit to help out someone with a faulty unit. From cursory reading i believe you can read 16v8s even with the security bit engaged, you just cannot access the logic matrix. |
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