The via6522 component written in System Verilog has been updated.
https://github.com/robfinch/Cores/tree/master/via6522/trunk/rtl
A small fix was made for timer interrupts. An interrupt is generated now only when the timer's count transitions to zero, not when the timer count value is zero. This is to avoid a continuous interrupt state brought about when the timer interrupt is cleared, But the count is still zero, causing the interrupt flag to be set again in the next cycle.

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