kernelthread wrote:
I think what you want is this:
/* Input pins */
pin 2 = clk;
pin [4,5,6,8,9,10,11,15] = [D0..7];
/* Output pins */
pin [16,17,18,20,21,22,24,25,27] = [Q0..7]; /* Q output */
/* Logic */
[Q0..7].L = [D0..7]; /* Each Qi is a transparent latch with input Di */
[Q0..7].LE = clk; /* Each Qi is a transparent latch with enable connected to clk - follows input when clk low, latched when clk high */
Thanks very much! As 'easy' as extensions seem to be, my brain still does not deal well with them and I didn't realise it was that simple.
[edit] Did you manage to get this simulated at all? WinSim doesn't seem to like it (what a surprise) with no results for Q0..Q7. 35 warnings come up when there is a .SI file (see below) so definitely a simulator issue.
No errors or warnings that I can find in the actual files. I'll keep looking, but this might be just a limitation of WinSim. I just love WinCUPL sometimes ...
The file being compiled is called OctalDlatch.pld and the header is the same in the .SI file:
Code:
Name OctalDlatch;
PartNo C;
Date 17/07/2021;
Revision 01;
Designer tst;
Company tst;
Assembly None;
Location None;
Device f1508ispplcc84;
ORDER: clk, D0..D7, Q0..Q7;
VECTORS:
0 'A0' ********
1 'A1' ********
0 'A2' ********
1 'A3' ********