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PostPosted: Wed Jan 26, 2022 10:33 pm 
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Hi

I have been wondering what 6502 core is the fastest? E.g. with respect to the number of instructions per second? Are there any that can do or exceed 1 instruction per cycle?


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PostPosted: Wed Jan 26, 2022 11:12 pm 
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John Kortink (Windfall) got his core to at least 420 effective MHz (on a 200 MHz clock) with premium hardware here, which seems to be slightly less than one instruction per cycle on average. I'm reasonably sure that Arlet's core is the lightest around here, but that's a different measure. In the linked thread, John reported Arlet's core at 230 MHz (on similar premium hardware) with "authentic" cycle-per-instruction behavior.

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PostPosted: Fri Jan 28, 2022 3:51 pm 
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I am not sure what the term effective MHz means, but it looks like he managed 1 cycle per instruction for some of the opcodes.

Has anyone tried more that 1 instruction per cycle?


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PostPosted: Fri Jan 28, 2022 4:45 pm 
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kakemoms wrote:
I am not sure what the term effective MHz means ...

I think it's an external measure of performance in a typical benchmark (whatever that is), and is affected by the clock speed and the cycle-per-instruction ratio. When he stated 420 MHz on a 200 MHz clock, I think he is saying that his core is on average executing 2.1 times more code per clock than an "authentic" 6502 can. Please correct me if I'm wrong.

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PostPosted: Fri Jan 28, 2022 4:56 pm 
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That's my understanding too.

As noted, then, John managed single-cycle for a lot of instructions, but not for all. And the large amount of machinery used brought down the clock speed from a small lightweight core, namely Arlet's. That's not too surprising. The large complex core was still a net win though, for overall performance.

I suspect this core of John's is the best yet, for instructions per clock. It might be best yet for absolute performance, on the particular FPGA he has, for a hardware implementation. (The nature of modern commodity CPUs is such that an emulated 6502 can be faster still. Of course that's on custom silicon with a very complex implementation.)

It would be interesting to see another attempt at a high-performance 6502, of course.


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PostPosted: Fri Jan 28, 2022 7:34 pm 
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kakemoms wrote:
I am not sure what the term effective MHz means, but it looks like he managed 1 cycle per instruction for some of the opcodes.

Has anyone tried more that 1 instruction per cycle?

Just feed multiple instructions to multiple execution units.

Not yet, I think. I may do it some day if no one else does. It seems like both an interesting and nightmarish exercise.


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