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WinCUPL, 22v10's suggestions and fun
http://forum.6502.org/viewtopic.php?f=10&t=6436		 Page 1 of 1
Author:  grantb5 [ Tue Jan 05, 2021 1:09 am ]
Post subject:  WinCUPL, 22v10's suggestions and fun
Hi, First time posting, long time 8-bitting (6502, 6800, 6809, 6811, 8051, 6303).

Goal is to remake a memory bank latch and some address decoding in an ATF22v10C-15PU, but right now I'm trying to just build a 74LS378 in the 22v10 as a first step. The 74LS378 chip works in the TTL version of the bank switcher. I'm not a master of PLDs by a long shot!

So, the LS378 is just a 6-bit latch with an active low G* (G not ... how do you guys do it here?) latch enable and latching is done on the positive going edge of CLK.

https://www.jameco.com/Jameco/Products/ ... 287295.pdf

I started down a weird path using just 22v10 logic (no flip-flops) and then later using the flip-flops once I learned more. I found stuff that works, but I'm not "confident", put it that way.

The logic-only version of a 1-bit latch (after much hair pulling) turned out to be:

Code:
/* Inputs */
Pin 2  = LE;
Pin 3  = !CLK;
Pin 4  =  D0;

/* Outputs */
Pin 23 = Q0;     

/* Logic: Mux  (internal variable Dx0) */
Dx0 = (!LE & D0) # (LE & Q0);

/* Manual flip-flop */
Q0 = !(Q0N # (!Dx0 & CLK));
Q0N = !(Q0 # (Dx0 & CLK));


For some odd reason this works, even though the CLK is opposite polarity. It does not work if I flip it (Pin 3 = CLK;). I'm not sure how to reconcile this, but I have a cheapie Chinese TES200 logic tester and it PASSES (cough, cough). ( https://www.brightwinelectronics.com/te ... odule.html )

Then I tried using the flip-flops and I came up with this.

Code:
/* Inputs */
Pin 1 = !CLK;
Pin 2 = LE;
Pin 4 =  D0;

/* Outputs */
Pin 23 = Q0;     

/* Logic: */
Q0.d = (!LE & D0) # (LE & Q0);


This also works, but on the tester it FAILS!

It would be nice if this was less of a mess, worked and maybe passed the tester (which does pass a true 74LS378 by the way). Suggestions?!

Finally, are there housekeeping things to do on a 22v10? I left .sp and .ar out and lived with the warnings. What about power up conditions?

Thanks!!
Author:  BigDumbDinosaur [ Tue Jan 05, 2021 5:30 am ]
Post subject:  Re: WinCUPL, 22v10's suggestions and fun
grantb5 wrote:
I'm not sure how to reconcile this, but I have a cheapie Chinese TES200 logic tester...

A basic logic probe is likely more trustworthy than the TES200. :D A logic probe is what I would be using, since it's simple combinatorial logic you are implementing.

Quote:
Finally, are there housekeeping things to do on a 22v10? I left .sp and .ar out and lived with the warnings. What about power up conditions?

.ar means asynchronous reset and would be used if you wanted to guarantee a specific flip-flop state following system reset. It would mean defining an input pin as the reset input and then writing an equation to tell the GAL to perform an asynchronous reset on any flops you've defined whenever your reset input is asserted. The data sheet is your friend.

With that said, the actual 74x378 does not have a reset input, which means the device was not guaranteed to be in a specific state at power-on. If you are attempting to faithfully emulate the '378 then your GAL logic shouldn't implement anything that wasn't in the real McCoy.
Author:  grantb5 [ Tue Jan 05, 2021 3:37 pm ]
Post subject:  Re: WinCUPL, 22v10's suggestions and fun
Thanks. I wasn't clear on the power-on situation, so that's good to know.

I have a scope but it's finicky as hell and my test circuit is breadboard. I will play with it some more. Any thoughts on using the built-in flip-flops (and dedicated CLK input) versus the equations?

I'm using the g22v10 as the device, versus p22v10, but no idea why. :?

Are there any other configuration/fuses I should be looking at? Assuming my programmer does what I tell it to. I have a Xeltek that will program it, but not verify and I have a Galep-5 that does both (and it verifies those programmed on the Xeltek).
Author:  BigEd [ Tue Jan 05, 2021 3:52 pm ]
Post subject:  Re: WinCUPL, 22v10's suggestions and fun
(Welcome!)
Author:  Sheep64 [ Tue Feb 16, 2021 3:52 pm ]
Post subject:  Re: WinCUPL, 22v10's suggestions and fun
grantb5 on Tue 5 Jan 2021 wrote:
active low G* (G not ... how do you guys do it here?)


I'm glad you asked. People use a variety of incompatible notations including but not restricted to !FOO, ~FOO, ¬FOO, /FOO, \FOO, FOO\ and /FOO\. The hardware experts seem to prefer /FOO while some of the programmable logic experts seem to prefer !FOO.

(From my perusal of the PHPBB source code, it might be preferable for administrators to create a bespoke overbar tag in the BBCode section of ACP [Adminstration Control Panel?]. The overhead is minimal and the upgrade scripts take great care to preserve custom tags. I also discovered that PHPBB is a shockingly good example of PHP. Given the reputation of PHP, I expected a disaster.)

grantb5 on Tue 5 Jan 2021 wrote:
I found stuff that works, but I'm not "confident", put it that way.


That's a familiar sentiment. It is good to know your limits or under-estimate them. Indeed, some good advice I received was to pick a project you believe has 80% success. By this method, you will spend about 1/3 of your time honing familiar skills, about 1/3 of your time on foreseen problems and about 1/3 of your time on unforeseen problems. From this, you will have the most variety and learn the most. So, extend a little outside your reach but not too far.

grantb5 on Tue 5 Jan 2021 wrote:
Are there any other configuration/fuses I should be looking at?


The most recent versions of 74 series logic have sharper edges and ringing which can induce multiple transitions; especially in older edge triggered logic. Programmable logic may also have sharp edges which can be dulled in settings. This might make your implementation function less like 74AC and more like 74LS.

You may also have voltage incompatibility or power distribution problem. When breadboarding, some people use thicker wires for power and ground. If you don't have thicker wires, you can double wire power and ground. Indeed, double wired power is most likely to compensate for a dodgy breadboard. That might be ineffective superstition but it certainly won't hinder.
Author:  BigDumbDinosaur [ Tue Feb 16, 2021 7:25 pm ]
Post subject:  Re: WinCUPL, 22v10's suggestions and fun
Sheep64 wrote:
The most recent versions of 74 series logic have sharper edges and ringing which can induce multiple transitions; especially in older edge triggered logic. Programmable logic may also have sharp edges which can be dulled in settings.

Something to keep in mind is GALs produce TTL output levels, not CMOS.
Author:  grantb5 [ Wed Feb 17, 2021 3:01 pm ]
Post subject:  Re: WinCUPL, 22v10's suggestions and fun
Thanks, this is for a mid-80's mostly 74LS circuit. I rebuilt my test setup on a soldered proto board. Solderless breadboards and "dupont" wires always seem really poor to me, so I gave up on that.

I haven't had much time to get back on it, but first job is to nail down this latch-with-enable (gated-latch, whatever you call it). I need to scope it versus the data sheet and make sure the setup and hold times are OK, no glitches, etc. The rest is combinatorial logic that may or may not fit in the part. I have enough pins though. Just.
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