Thank you for the monitor source. Your monitor is significantly more sophisticated than what I have in mind. I need the 4 basic functions of 'load', 'display', 'change' memory, and 'go'. Typically I also have a 'list' function that lists specified memory region as S record or Intel Hex. This way the memory can be restored with a 'load' command. Memory diagnostic is sometimes useful, and I've found filling memory with NOP instructions serves an useful debugging function.

Proto65 depends on the IDE drive to serve as system EPROM so there are more IDE related functions such as sector read, sector write, save memory images, restore memory images, format disk, install system programs, and recall & run specified system program.

Bill

I made a small change in CPLD to drive the 6502 clock with a CPLD output. That seems to stabilize the design significantly. I ran Conway's Life for 2 hours successfully at the nominal 14.7MHz. I'm also able to run the board at 20.28MHz, but CPLD is getting quite warm so I didn't try higher clock frequency beyond 20.28MHz.

At this point the rev0.2 development is completed. I have created a homepage for rev0.2 and put design info and software there.
https://www.retrobrewcomputers.org/doku ... proto65r02

The next step is adding VGA circuitry. I'll start with a monochrome, character-based 64 columns X 48 rows display with 8x8 font. That may be all I can accomplish with this CPLD. I will add several new components and lots of wires so there is some chance I'll blow up this prototype board. That's another motivation for capturing all the designs to layout a replacement PC board for the worst case scenario.
Bill

After a month of detour to work on an offshoot of this project, CRC65, I'm ready to come back to this project. I have done quite a bit of software for CRC65, so I do want to reuse these software for this project as well. CRC65 is a simpler design, so by making the design compatible, more CPLD resources would be free up for the VGA circuitry.

The goal of rev0.3 is adding a monochrome, text-based VGA display and a PS2 keyboard. Monochrome text-based VGA is about the simplest VGA video; it needs minimal amount of video memory. The video RAM is an inexpensive 4K dual port RAM (IDT7134) that maps to 4K of 6502's high memory. The other side of the dual port RAM is under the control of CPLD which generates the horizontal and vertical syncs and video data stream at 25.175MHz pixel clock rate. 4K video RAM should give me 1K of 8x8 fonts and 3K of character memory (64 columns x 48 rows)

So Proto65 rev0.3 tasks are:
* Change the design to be compatible with CRC65 software,
* Add a video daughter board that contains a 4K dual port RAM, VGA connevctor, PS2 connector, and 25.175MHz oscillator,
* Add VGA timing generator to CPLD and convert data in dual port RAM to VGA video stream, and
* Add PS2 keyboard input capability.

Picture shows the video daughter board married to Proto65 board.

Here we go...

I have revised Proto65 CPLD design so it is now compatible with existing CRC65 software. Schematic of the CRC65 compatible design is attached. The CPLD resource utilization is now 109 macrocells (57% utilized) instead of 142 macrocells (74% utilized). This should free up enough macrocells to implement the VGA timing logic.

Everything is wired up and smoke tested; 6502 still booted and responded to console command, so miraculously I didn't break anything. Now I need to do serious update to the CPLD to enable the VGA output.

Here is the first picture of the text-based VGA display. The display is 64 column by 48 lines. Each text character is 8x8 pixel so the display area is really 512x384 instead of VGA's 640x480. To take advantage of VGA's 480 lines and to improve readability of texts, I added 2 blank lines per 8 lines, so each character is effectively 8 pixels wide and 10 pixels tall with the bottom 2 rows of pixels always blank. This makes the effective display area as 512x480.

The fonts in the picture are 7x7 with one blank row at the bottom and one blank column at the right side. I can make it a little bit bigger, 7x8, since there are always two blank rows between each line of text.

The monitor is a 9" diagonal LCD monitor with VGA input. It is commonly used as a car backup monitor.

The base address of dual port RAM is at 0xD000. The text memory is from 0xD000-0xDBFF and font table starts from 0xDC00-0xDFFF. As far as 6502 is concerned, the dual port RAM appears as a regular memory. It can execute program, store data and pass memory diagnostic; memory can be read or written at any time. The other side of the dual port RAM is read-only and accessible by state machine in CPLD only. The VGA state machine in the CPLD is effectively 2 cascaded counters, modulo-800 counter driving a modulo-520 counter. Horizontal sync, vertical sync, and associated front porch and back porch are derived from outputs of the modulo 800 and 520 counters. One design complication is the CPLD state machine reads the text memory first then uses the value to index into the font table to look up the bit map associated with the character. The dual port RAM access time is 35nS and these two accesses occur over a character time which is 320nS at 25.175MHz, so plenty of time to accomplish double read access.

The CPLD is now 89% utilized,. plenty of room for PS2 keyboard interface.
Bill

While I appreciate the element of fun, and cited as motivation since my first message, fun can be maximized with layout or otherwise soldering down your design.

To quote more than one game, "Checkpoint!"



I believe that it is possible to drive eight chains of WS2812 with 5MHz 6502. This is one of the many uses for a binary matrix transpose.



Yup, those things are bright and energy hungry. I bought a chain of 200 and then realized that I don't have a suitable PSU for them. Doh!



Have you sketched how to implement such a device? The shift chain requires a resistor-capacitor network and a comparitor (which itself may require 31 transistors). This converts a Morse code style pulse into zero or one. This would be fed into a chaim of 24 or 32 one bit latches and then the far end of the chain has to recreate pulse widths for the next device. Another resistor-capacitor network sets the data live in a second set of latches after a period of inactivity. (Effectively, three or four 74HC595 chips.) An internal oscillator, eight bit counter and three sets of eight bit binary comparitors would be suitable for PWM. Smoother operation requires the top bits of the eight bit binary counter to be selectively inverted. This staggers three or four channels each by 90 degrees. And finally, all of this has to be shielded from the high intensity light sources otherwise the photo-electric effect will stop the circuitry working as intended. This is yours for 10 cents or less. Yup, that's quite amazing.



If a bit error occurred in Conway's Life, would you notice?

_________________
Modules | Processors | Boards | Boxes | Beep, Beep! I'm a sheep!

This 9-second YouTube video is Game of Life running on Proto65's VGA display. The previous screen is "dissolved" pseudo randomly one byte at a time. The Game of Life ran for 256 generations in about 6 seconds which is quite a bit faster than it ran in the 128x64 OLED display. This is because its universe is smaller, 64 x 48, instead of 128x64 and more importantly, the GoL universe is on the 64x48 video RAM itself and the software manipulated data directly on the video RAM without having to bit-bang the display data over the I2C bus. Since the display is taken care of in hardware, this Game of Life program is small, about 430 bytes.

https://youtu.be/iMYlma55jus

Bill

Since I was able to overclock CRC65 to 29.5MHz and Proto65 is the same design as CRC65, the question is whether this board with the additional loading of DPRAM and long wires from 6502 to DPRAM can also run to 29.5MHz? The answer is NO. However, it CAN run at 25.175MHz IF the voltage is maintained at 5.1V. At 25.175MHz the current consumption is 400mA@5.1V EPM7192S is fairly warm, but I still can keep my finger on it. With better board design, there is a chance the whole system can run at 25.175MHz.
Bill

That's a very impressive speed! Beware though, that 'working' is not such a binary state: until you've run every application you might want to, with every data input combination, you don't know for sure that the system will work. (It's for this reason that speed testing is normally done with some margin, in the hope that backing off from the speed tested at will be enough.)

We had an example, I think it was with carry out from a subtraction, where one specific opcode in one situation failed at a lower speed than anything else. In other words, we found a critical path. Of course we still don't know if that's the worst case.

(It might be that you know all this!)

Ed,
Thanks for the comments. I have some familiarity with the hazards of overclocking. As a professional engineers in my previous life, overclocking was done strictly for design margin tests and I had only overclocked 1 speed grade (33%). End products were delivered fully within the manufacturer's specifications since we were dealing with mission-critical programs.

As a hobbyist making retro computers, the hazard of overclocking is overshadowed by murky supply chain and used parts of unknown provenance. Testing is really the only way to overcome these unknowns and we are all aware of the limitation of testings. Nevertheless, it is important to run the hardware through various test and application software. My test suits are memory diagnostic, EhBASIC benchmark, CF diagnostic, and Klaus' test suits. It is limited testings and no way to know whether critical paths were exercised. Fortunately no mission critical programs will be involved with these retro hardware other than burning up breads in my retro toaster oven!

BIll

Returning to this old thread after two years because I've had success with PS2 interface. Recently I have added additional features to VGARC (a Z80 add-on board) that requires larger CPLD to realize. Proto65 has a large CPLD that can accommodate both PS2 interface as well as the additional video functions.

PS2 is ported and working. It has a status register to indicate keyboard data is ready and a buffered data register. The added video functions are hardware cursor which is a 8-pixel long, 2-pixel wide underscore activated by setting bit 8 of a text. (Text is 7-bit mapped to 128 fonts, the 8th bit was not used previously.) The second added functions is hardware scrolling that is accomplished by writing values 1 to 47 to a register to scroll up screen text by 1 to 47 rows. The rows scrolled off the top of screen are roll around to to the bottom of the screen. For a typical console application, the top row is blanked out and screen scrolled by one row, so the rolled over top row shows up as a blank line at the bottom of screen. Scrolling does not change the video RAM mapping; it changes how the RAM contents are display on the screen; so software needs to keep track of how many rows have scrolled in order to display new contents on the desired location on the screen. For an example, a stationary status bar at the bottom-most row of the screen needs to know how many rows were scrolled in order to write the updated status information at the same bottom-most row of the screen.

I added a scrolling routine outside of this Game of Life that starts off without scrolling for a few seconds then the screen is scrolled up 5 rows, back to 0, then down 5 rows and repeat. The main program doesn't know about rows being scrolled up and down. It operates on the same Universe resided in the same locations of video RAM. Scrolling changes where data are displayed on the screen but not its locations in video memory. (click on the picture to start the video)

Anyway, I hope to evolve this hardware to a standalone 6502 with text VGA and PS2 keyboard but still have serial connection to workstation for software updates. I hope to develop some games (Tetris and Space Invader are obvious ones) and applications like screen editor and DOS/65
Bill

Hi Bill
Just wondering if some this would apply to the CPLD trainer and a VGA6448 version 1 or 2. The CPLD trainer has a PS2 connector and the VGA6448 can do the output but I guess there is no CF card or DOM.
Perhaps you are going to create a whole new board rather than the 2 board CRC65 and VGA6448.
Anyhow it's interesting to see what develops.

Larry

Larry,
Proto65 is an experimental vehicle to explore new ideas because it has a fairly large CPLD (EPM7192S) with unused logic. If I were to create a new board with EPM7192S, it probably will look like 6502 version of Z80all--a all-in-one computer with expansion bus plus a CPLD with spare capacity for experimentation.

Hardware scroll and cursor are nice capability, but VGA6448 can do the equivalent functions in software so I still see CRC65+VGA6448 as my main path to the standalone 6502 computer. VGA6448 is mainly a monochrome text display with limited graphic capability, I do have a color graphic version for CRC65 that is undocumented other than one picture here.

I think Trainer with 6502 may be more versatile if a 3-slot bus extender is added. This will give it 4 expansion slots to add CF disk, VGA6448, sound, and quad serial board.

The one 6502 board (actually 2-board stack) I have on the drawing board is production version of 36MHz 6502. I'm shooting for 40MHz operation, but even at 36MHz it can beam race SVGA (800x600) or it can do DOS/65 really fast plus spare capacity in EPM7128S CPLD for general experiments.

In reality these are more talks than actions; Spring is coming very quickly so I'm more likely out gardening in a month or so.
Bill