I finished the (hopefully) final rewrite of the microcode control bits for the address bus, incorporating the F7MUX, and also did some more instantiations in the Spartan6 design elements, including this ALU shifter mux that worked the first time, even though I wrote down the hex INIT strings without first making a table.
Code:
* op function
* ===============================
* 0?-- | unmodified adder result
* 10-- | adder shift left
* 11-- | adder shift right
*/
LUT5 #(.INIT(32'hf0ccaaaa)) out0(.O(OUT[0]), .I0(add[0]), .I1(SI), .I2(add[1]), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out1(.O(OUT[1]), .I0(add[1]), .I1(add[0]), .I2(add[2]), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out2(.O(OUT[2]), .I0(add[2]), .I1(add[1]), .I2(add[3]), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out3(.O(OUT[3]), .I0(add[3]), .I1(add[2]), .I2(add[4]), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out4(.O(OUT[4]), .I0(add[4]), .I1(add[3]), .I2(add[5]), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out5(.O(OUT[5]), .I0(add[5]), .I1(add[4]), .I2(add[6]), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out6(.O(OUT[6]), .I0(add[6]), .I1(add[5]), .I2(add[7]), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out7(.O(OUT[7]), .I0(add[7]), .I1(add[6]), .I2(SI), .I3(op[3]), .I4(op[4]));
LUT5 #(.INIT(32'hf0ccaaaa)) out8(.O(CO), .I0(C8), .I1(add[7]), .I2(add[0]), .I3(op[3]), .I4(op[4]));
The LUT5 is a nice thing to use, because on the Spartan 6 this means you get 8 LUTs in a slice instead of 4.
The address bus logic is now fully instantiated, as well as the main ALU path, but not yet the random logic involving the flags and BCD adjustment. Still need to do the microcode control logic, flags, and register file.
Slice count is 44 right now, 60 flip flops, and 134 LUTs. The slice/LUT ratio indicates that slice count could go lower with better packing. Something in the 30's could be possible, maybe.
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