So, I'll be the first to admit that I'm still mostly new to using CPLDs... having only done one so far, with some help some the group here... notably Peter (CBSCPE), who provided some great input and some coding changes when I was working with an Atmel ATF22V10CQZ over 2 years ago.
I've working on an adapter for my C02 Pocket SBC which has a 16-bit IDE port and a DS1511Y RTC. I'm using an ATF16V8BQL CPLD to manage all of the I/O decode and drive the high-byte read and write latches for the 16-bit data port as well. I seem to have a working CPLD at this point, but I'm looking for a sanity check. The datasheet shows different modes for the ATF16V8, which aren't 100% clear (to me at least).
In any case, I'm using a single I/O select which is 32-bytes wide which drives an input on the CPLD along with 5 address lines (A0-A4), a phase 2 clock aligned Read and Write signals. I'm grounding the OC line and have a Clock attached to the CLK input, but I don't think I actually need it. I'm using addresses $00 - $13 for the RTC, locations above $13 are not used. Locations $14-$15 are for the high-byte read/write latches. Locations $16-$17 are for CS1 on the IDE drive and locations $18-$1F are for CS0 on the IDE drive.
I've burned a CPLD and have it on a breadboard with pull-up resistors and switches to set the address and R/W lines, plus LEDs and resistors on the output to show the status of the lines. It seems to be working... the Simulator also follows what should be. However, I was hoping to use the OC line with the I/O select, as it "should" enable or disable all of the outputs , or so I thought. I could never get that to work regardless, so I just grounded and used another input for the select line. I'm hoping some with more knowledge and experience on this can give me some feedback/guidance on what I' m doing (right or wrong). I'm still thinking I don't need a clock signal on pin 1... but I'm not certain.
Here's the code for WinCUPL:
Code:
Name IDE-RTC ;
PartNo 01 ;
Date 1/04/2020 ;
Revision 01 ;
Designer KM ;
Company Analogue Technologies ;
Assembly SBC2 ;
Location ;
Device G16V8MS ;
/* *************** INPUT PINS *********************/
PIN 1 = CLK ; /* */
PIN 2 = A0 ; /* */
PIN 3 = A1 ; /* */
PIN 4 = A2 ; /* */
PIN 5 = A3 ; /* */
PIN 6 = A4 ; /* */
PIN 7 = !MRD ; /* */
PIN 8 = !MWR ; /* */
PIN 9 = !SEL ; /* */
PIN 11 = !OC ; /* */
/* *************** OUTPUT PINS *********************/
PIN 18 = !UBWE ; /* */
PIN 16 = !UBRE ; /* */
PIN 19 = UBWL ; /* */
PIN 17 = UBRL ; /* */
PIN 12 = !CS0 ; /* */
PIN 13 = !CS1 ; /* */
PIN 15 = !RTC ; /* */
PIN 14 = !HBT ; /* */
/** Declarations and Intermediate Variables Definitions **/
FIELD ADDRESS = [A4..0];
RTC = SEL & ADDRESS:['h'00..13];
HBT = SEL & ADDRESS:['h'14..15];
CS1 = SEL & ADDRESS:['h'16..17];
CS0 = SEL & ADDRESS:['h'18..1F];
/** Logic Equations **/
UBWE = MWR & SEL & ADDRESS:['h'18..18];
UBRE = MRD & SEL & ADDRESS:['h'14..14];
UBWL = MWR & SEL & ADDRESS:['h'15..15];
UBRL = MRD & SEL & ADDRESS:['h'18..18];
Note: HBT is just defined as the high byte latch address range, but it's not connected to anything.... more of a test line from the CPLD.
If anyone has some suggestions on a better way to do this, I'm open to them. I'm currently modifying the adapter board and replacing the 44-pin IDE connector with a Compact Flash socket, so I'm just using the same basic layout and the same CPLD setup. Thanks.