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A/V SBC with Multiple 65xxx CPUs http://forum.6502.org/viewtopic.php?f=10&t=5867	Page 1 of 5

Author:

ElEctric_EyE [ Sat Dec 14, 2019 10:52 pm ]

Post subject:

A/V SBC with Multiple 65xxx CPUs

Board Description:
The 4 layer board measures 2.5" (63.5mm) x 4.5" (144.3mm). It's a design that has evolved from past projects that have primarily focused on video. This new board can also display 1080p 16-bit 5-6-5 RGB video using a VGA connector, but now can also accommodate audio I/O.
There are 2 Spartan 6 FPGA's, each of which can control up to 2 4Mx18 250MHz NBT (No Bus Turnaround) SyncRAMs wired to form 8Mx18. [more to add here]

All IC's are powered by 3.3V with 5V needed for the Audio and USB. A rather tight voltage range of 5V-5.5V @5 amps is needed for the main power supply input. Close to 3 amps (max) are used by the SyncRAMs alone (@250MHz).

The I2C bus:
1) A programmable CMOS crystal oscillator with a frequency range of 100kHz to 212MHz. Boot address: $55
2) A resistive touchscreen controller. Boot address: $48
3) Digital audio transceiver. Boot address: $80

The SPI bus:
1) SD Card controller.
2) 256Mb FLASH.

I/O Connectors:
1) 2mm x 5.5mm 11Amp main power receptacle input.
2) 4 pin FFC connector for resistive touchscreen input.
3) VGA output.
4) JTAG for programming FPGA's. Digilent HS-1 Rev A JTAG programming cable is used. Digilent HS-2 & HS-3 are currently available.
5) USB for keyboard input, PC communication.
6) micro-SD card for storage, data exchange.
7) SPDIF receiver module. Up to 216kHz In.
8) SPDIF transmitter module. Pass thru.
9) SPDIF transmitter module. Out.
10) 3.5mm stereo receptacle. 2x analog inputs to 24-bit ADCs @ 96kHz.

IC's and Package Styles:
FPGA's: Xilinx XC6SLX9. 144-pin QFP.
FPGA 8Mb SPI FLASH (PROMs): Winbond W25Q80DV. 8-pin WSON.
Synchronous RAM's: GSI Tech GS8640Z18. 100-pin QFP.
Digital Audio Transceiver: PCM9211. 48-pin QFP.
330MHz VideoDAC: ADV7125. 48-pin QFP.
Programmable Oscillator: Si514. 6-pin 5x7mm.
Touchscreen Controller: SX8651. 12-pin DFN.
USB to UART: MCP2200. 20-pin QFN.
FAT16/32 SD Card Controller: CH376T. 20-pin SSOP.
256Mb (32MBx8) SPI FLASH: S25FL256S. 8-pin WSON.

Onboard Linear Voltage Regulators and Filtered A/V Powers:
1) 3.3V @5A: TPS75633. Main 3.3V Power derived from main 5V input.
2) 2.5V @1A: MCP1826: FPGA VCCAUX. Power derived from main 5V input.
3) 1.2V @1A: MCP1826: FPGA VCCINT. Power derived from main 5V input.
4) 5V for analog audio section of the digital audio transceiver is filtered from the main 5V input through a 500mA ferrite bead and ceramic cap's.
5) 3.3V for digital audio section of the digital audio transceiver is filtered from the main 3.3V power plane through a 500mA ferrite bead and ceramic cap's.
6) 3.3V for the videoDAC is also filtered from the main 3.3V power plane through another 500mA ferrite bead and ceramic cap's.
[schematic soon]

Design Challenges:
The very first challenge was trying to stack the RAMs. After placing 1 RAM on the bottom and flipping the 2nd RAM to go directly behind it on the opposite of the board, I quickly realized the pin layout of the SyncRAMs easily accommodated this setup. Just a few pins needed special attention by adding traces. The rest of the address lines and data lines just required vias to connect to the other address and data lines respectively, direct pin to pin lineup is not necessary.
The second challenge, after adding the digital audio transceiver was finding room to place the pass thru SPDIF module. Currently it is on the opposite side of the board as the USB connector. This will require me to shave down the pins of the module after soldering so that the USB connector can sit more flush to the board. I'll also have to insulate the bottom of the USB connector as it is metal.
The next challenges were getting the SPDIF control signals to the Master Spartan 6 and the analog L & R inputs wired up between the barrel jack connector and the digital audio transceiver IC. The constraints of using 4 layers and size of the board forced me to use wire wrap for the control signals and shielded analog cable for the analog inputs.

First Design Concept:
The Master Spartan 6 has 35 I/O lines of communication with the Slave Spartan 6. For my conceived design, the Master will send RGB data to the Slave along with HSync & VSync and Pixel Clk. That leaves 17 I/O lines for commands between the Master & Slave Spartan 6's.
The Slave will then send out the RGB to the 330MHz capable videoDAC. The Slave can also communicate with a keyboard or a Windows PC via USB. This video setup will allow not only multiple page flipping but also video overlay. The video overlay is a concept I've proven using 5 Parallel Video Boards. 3 boards seemed to be the realistic limit due to some video pixel noise created from back-plane connectivity between the boards @148.5MHz. That design had no ability for page flipping and I abandoned it. So in this current design there are 2 video sources, 1 per FPGA, merged into one board. Hardware graphics in the 'rear' plane while character plotting on the front from the Master and Slave hardware plotters will be the first goal.

More Design Concepts:
Not all the IC's need to be on the board in order for it to be functional.
For example, if one just wanted SPDIF functionality, only the SPDIF Transceiver and Master Spartan 6 would be needed with just a few supporting ICs (Oscillator, FPGA PROM, Voltage Regulators, etc).
Another possibility, since the keyboard interface and video output are done by the Slave Spartan 6, you could have a terminal? or maybe assembler? In addition, this would require at least 1 SyncRAM for video output and the videoDAC.
[more to add here]

NOTE: This is a work in progress. Look here for critical updates like pics, FPGA constraints, parts list, etc.
Block Diag made with yEd. Extended pics taken with Techsmith Snag-It.

EDIT (1/9/20): Added Digilent JTAG programming cable details.

Attachments:

V1.5 Production.Top.Real.jpg [ 977.12 KiB | Viewed 2281 times ]

V1.5 Production.Bottom.Real.jpg [ 934.67 KiB | Viewed 2281 times ]

EPCB.jpg [ 158.43 KiB | Viewed 2308 times ]

Block_1.jpg [ 187.8 KiB | Viewed 2321 times ]

V1.5 Production. Bottom. Layer.jpg [ 1.81 MiB | Viewed 2380 times ]

V1.5 Production. Top. Layer.jpg [ 2.12 MiB | Viewed 2418 times ]

Author:

ElEctric_EyE [ Mon Dec 30, 2019 9:49 pm ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

Starting the soldering today using my hot plate that I've used years ago. It still works very well. There's an old thread in here in the Programmable Logic section about SMT reflow where I showed it off. It has the link to where I based the design. It has 1 thermocouple and 4 heating elements in a 1" thick 8"x6" block of aluminum. It takes about 30 minutes to get it to 200C from room temp. After that, the board goes on for about 5-10 seconds. To cool it down quickly I place it on an identical block of aluminum at room temp which quickly draws the heat away.

Attachments:

Hotplate.jpg [ 2.27 MiB | Viewed 2250 times ]

Author:

ElEctric_EyE [ Mon Dec 30, 2019 9:55 pm ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

I'm starting with the JTAG section as I've never used SPI FLASH to program the Xilinx Spartan 6. I've always used the Xilinx PROMs with no problem. So after soldering, I'm check out the connections using a USB microscope. And after looking at this pic, I've realized I forgot to add flux! Bad solder joints. Hopefully adding some flux after the fact and reflowing will refix the problem.

Attachments:

USB microscope.jpg [ 2.41 MiB | Viewed 2155 times ]

SPI FLASH QC.jpg [ 231.82 KiB | Viewed 2251 times ]

Author:

ElEctric_EyE [ Mon Dec 30, 2019 10:45 pm ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

Attachment:

After flux.Cold joints.jpg [ 341.94 KiB | Viewed 2245 times ]

After flux. Did not solve the problem.
Here I've added the SMALLEST amount of Chipquick liquid solder. Some interesting pics.

Attachments:

Chipquick liquid solder close.jpg [ 494.86 KiB | Viewed 2245 times ]

Chipquick liquid solder far.jpg [ 415.7 KiB | Viewed 2245 times ]

Author:

ElEctric_EyE [ Mon Dec 30, 2019 10:52 pm ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

Final desired result, close enough anyway. 4th reflow. Not good. However, I am developing a SOP for IC's at least. Individual 0402 packages will be the real challenge, but I had no choice!
Now it's off the ultrasonic cleaner with a heated solution of Windex. Caveman make SMD boards

Attachments:

Liquid Solder reflowed.jpg [ 391.41 KiB | Viewed 2244 times ]

Author:	kakemoms [ Tue Dec 31, 2019 7:51 am ]
Post subject:	Re: A/V SBC with Multiple 65xxx CPUs
You may want to consider a two-step reflow process to get better solder joints. Going all the way to solder temperature at one step within a few seconds will give you all sorts of problems. One of them is "splatter" of the solder which will remove the solder from one point and deposit it all around. I believe that is what you are experiencing. One way to do this is to increase the temperature of the board more slowly. You can put your hotplate at a lower temperature and use some thermal resistance between the hotplate and your board. For example another PCB. That will bring your board up in temperature more slowly. You will then need to finish the reflow with a heatgun (or alike) to bring the components up to the final solder temperature. Keep the components at reflow for around 30 seconds and then bring the whole board down in temperature again. With a heatgun, the board will go down to the hotplate temperature, and then you can take it off (the hotplate) and let it cool. Try to prevent temperature shocks. You may want to look at this link (look under "reflow profile") to get a better understanding of what can happen if you shock your boards.

Author:	ElEctric_EyE [ Tue Dec 31, 2019 2:20 pm ]
Post subject:	Re: A/V SBC with Multiple 65xxx CPUs
I think you're correct, a hot air gun would probably help. Also, after watching some more videos I realized I need liquid solder. I'm using solder paste currently and it's preventing me from applying as much as I really need.

Author:

ElEctric_EyE [ Tue Dec 31, 2019 8:15 pm ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

So for the FLASH PROM's I just applied more flux and hit each pin with the soldering iron. I think that's what I'm going to wind up doing for everything. I tackled some 0402 passives using the hot plate and heat gun. The flux kept the parts from being blown away. Then I let it cool down, reapplied some flux and hit each end with the soldering iron with the slightest bit of solder on the end.

I'm almost done with the JTAG section. 4 0402 resistors have been soldered in, the DS1818's with internal 5.5K pull-up resistors are soldered in. I believe all that's left are the reset buttons, the FPGA's and the JTAG connector. Ah, and the voltage regulators which I still have to order.
Here's the schematic for the JTAG section. I realized I made an error on the silkscreen labeling the Master and Slave reset buttons. They're switched.

I'll have some more pics after I solder in the FPGA's.

Attachments:

JTAG.jpg [ 142.42 KiB | Viewed 2173 times ]

Author:

ElEctric_EyE [ Tue Dec 31, 2019 9:50 pm ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

144-pin .5mm QFP's are a breeze to solder in. There's enough solder already on the new board, so I've done exactly what I've done so many times in the past for these QFP's: Just applied flux, laid the IC on top and swiped a fine tip soldering iron, @450deg F, towards each pin. Nice, clean and neat. No hot plates, no heat guns, no liquid solder. I'll be doing the same for the 100-pin .5mm QFP SyncRams, if I get that far with this version of the board. The 0402 passives are the only challenge here I think.
Here's some pics after a hot ultrasonic bath in 91% Isopropyl Alcohol.

Attachments:

6x5 WSON pkg. FPGA FLASH PROM.jpg [ 198.33 KiB | Viewed 2165 times ]

0402.R7.close.jpg [ 213.93 KiB | Viewed 2165 times ]

0402.R6.close.jpg [ 169.89 KiB | Viewed 2165 times ]

144-pin .5mm QFP. close2.jpg [ 224.3 KiB | Viewed 2165 times ]

144-pin .5mm QFP. close.jpg [ 201.52 KiB | Viewed 2165 times ]

Author:

ElEctric_EyE [ Tue Dec 31, 2019 10:30 pm ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

Soldered in 2 of the 3 voltage regulators and also the main power in receptacle. The VGA connector was just snapped in for show. The point of this first stage is to verify JTAG programming. Putting in an order for some stuff. See you next year!~

Attachments:

12.31.2019.front.jpg [ 2.04 MiB | Viewed 2159 times ]

12.31.2019.back.jpg [ 1.12 MiB | Viewed 2159 times ]

Author:

ElEctric_EyE [ Wed Jan 01, 2020 12:52 am ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

Temp storage... Need a few parts.

Attachments:

Temp Storage.jpg [ 286.94 KiB | Viewed 2145 times ]

Author:	ElEctric_EyE [ Mon Jan 06, 2020 9:37 pm ]
Post subject:	Re: A/V SBC with Multiple 65xxx CPUs
I got the TPS756333 5A 3.3V linear voltage regulator, soldered it in, powered the board up and measured the 5V in, 1.2V, 2.5V and 3.3V. All are within spec. So tonight I'll finish off by scavenging the JTAG connectors from an old PVB board and I should be able to test the programming of the FPGA's using ISE14.7. This is two steps forward. I did have a 1 step backwards moment when my main desktop computer failed to boot on Jan 2nd. Jan 1st I was away. Very very curious timing for this failure! However, I was prepared as I backed up everything to bluray when I had the boards made weeks prior and can proceed with JTAG testing on another computer very soon! Xilinx has updated ISE 14.7 for Win10 but it's only good for the Spartan 6 which is fine in my case.

Author:	BigEd [ Mon Jan 06, 2020 10:13 pm ]
Post subject:	Re: A/V SBC with Multiple 65xxx CPUs
Good save with the backups!

Author:	ElEctric_EyE [ Tue Jan 07, 2020 8:58 pm ]
Post subject:	Re: A/V SBC with Multiple 65xxx CPUs
BigEd wrote: Good save with the backups! I've learned. But still learning. My backup RAID5 server is on that computer that is down. It has operating system images, ISE images and project files... Next plan is to make that RAID5 array mobile. So I must download many GB worth of data for ISE. 2nd attempt today after 7GB yesterday when I tried installing Xilinx' newest Windows 10 version but it runs under a virtual machine which will no doubt slow down the entire ISE environment. I can't tolerate that. So I'm downloading the previous version for Win7 and trying this fix again. This will take another 3hours to just download.

Author:

ElEctric_EyE [ Thu Jan 09, 2020 12:01 am ]

Post subject:

Re: A/V SBC with Multiple 65xxx CPUs

Still working out the ISE 14.7 install... iMPACT is not being installed for some reason, so I can't test the JTAG yet. Seriously pissing me off,,, I have to bring my old machine back up and reanalyze this whole PC failure situation.
Today I've installed the JTAG connector and took 2 pics with the 5V 11A power connector. That power is coming from an old ATX switching power supply. Plenty of current and good regulation. Be patient with this old geezer!

Attachments:

5VIn&jJTAG2.jpg [ 1.69 MiB | Viewed 1988 times ]

PWR&JTAG.jpg [ 1.5 MiB | Viewed 1988 times ]

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