Hi all,

I’ve finally dipped my toes into the FPGA pool for the purpose of converting existing schematics onto the FPGA using Verilog on a TinyFPGA-BX. I’m slowly getting the hang of Verilog and replicating 74-level gates into modules I can use for a larger glue-logic circuits to be used in my (physical) 6502 / 6522, etc. SBC chip project.

This might not be the best way to go about building a circuit from older schematics, but it’s the path I’m taking for now getting started.

As I’m creating my library of “virtual” 74-level chips, my first question is, do I need to implement nanosecond delays replicating what a physical 74LS04 (for example) would give? The schematics I’m using are based on physical chips so naturally there would be delays within each chip that might mess up a physical 6502/6522, etc circuit in this hybrid approach.

Thanks for any assistance and input!
Chris Z

Most HDLs like Verilog and VHDL, for example, are primarily designed for simulation. A significant portion of these languages are dedicated to supporting simulation. Much of the language cannot be used for synthesizing hardware. One of the elements of these languages that is not synthesizable are the delay statements. In both Verilog and VHDL delays are only used in simulation, and are ignored by the synthesizer. Your HDL synthesizer / compiler should have a description of the constructs / statements that are synthesizable. I would recommend finding and studying that documentation; it will prevent much frustration as you become more proficient with RTL descriptions of circuits that you want to develop.

I use the delay statements for two purposes: (1) to show that the signals follow the clock edge, and (2) to avoid some faults that I've observed with several simulators as they try and resolve signal transitions of complex circuits. I never use delay statements to insert physical delays in my designs.

Generally speaking, your designs should work without any delay statements included in your synthesizable HDL source code. If you wish to represent the expected delays of your physical circuits, i.e. those in your FPGA, for display purposes, then including the delay statements will provide that in whatever timing diagrams you produce. However, do not confuse those delays as being synthesized into the FPGA by the synthesizer. The synthesizer does not determine in any way the physical delays of the circuits in the FPGA or CPLDs.

If physical delays are needed in the synthesized circuits, then specific library elements for the target device must be invoked. The delay statements themselves will not be used for that purpose by the synthesizers targeting FPGAs / CPLDs. Also, do not construe a chain of gates, like a series of inverters / buffers, as being a means by which delays can be introduced into synthesized FPGA / CPLD circuits. In almost all cases, the synthesizer will optimize those chains away, or collapse them into a single Look-Up Table (LUT). There are ways to force the synthesizer to implement chains of gates like inverters or buffers, but those techniques are not ordinarily used in HDL based designs.

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Michael A.

When I was playing with VHDL I built models of some logic chips which allowed the timing to be passed in as a compile time parameter. Its only useful in simulation.

http://www.obelisk.me.uk/vhdl/74series.html
http://www.obelisk.me.uk/vhdl/cmos.html

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Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

Michael - Thanks. That's what I kind of thought - that delays were only applicable in simulations, not in synthesis.

Andrew J - that's a nice collection of 74 series logic. I'll compare your VHDL to my Verilog and see how far I was off.

Chris Z

My small tip:
If you want real delays, use a high-speed clock and a counter. Remember to only trigger counter on pulses, so use a two-level approach with a pulse generator in between.

For example, if you use a 100MHz clock as a basis, use the clock edge to trigger a pulse. Then use the pulse to increase the counter.

Then you can add in different modules that are started at different counter values (E.g. 0, 1, 5, 11, whatever..). It will give you a 10ns resolution on delays between the modules.

If you don't understand any of this, I can post some example code once I get back to my PC.

Edit: Here is a code segment that uses a clock clk and a counter clk_slow_cnt to trigger a pulse clk_slow_ena in order to output a slower clock clk_slow.



This works nicely and I have been using it for some time. You can then use clk_slow_cnt or another clock to trigger different events that needs to happen at different phases/times in the clk_slow period.

I like your approach to learning HDL... Data buses will be your greatest challenge I think. After that, the sky is the limit.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502