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PostPosted: Wed Jun 26, 2019 6:42 pm 
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Sorry, I feel stupid asking this but sometimes simple math gets stuck in my head.

So, let's say I'm shooting for a monochrome VGA display of 640x480 pixels. That's 307,200 bits per frame. At 60 FPS, that's 18,432,000 bits drawn by the VGA hardware every second.

If I divide that by 1,000 (for milliseconds) and again by 1,000 (for nanoseconds), I get 18.432 pixels drawn for each nanosecond.

Which means that whatever RAM chip I used, it would have to be able to update the address and fetch the data in around 17 nanoseconds.

12ns SRAM is not hard to find in DIP format. But it's limited to 32KiB.

This doesn't seem right to me. That's for only monochrome. Did early VGA graphics (8bit/256 color) graphics have super fast RAM?

What am I missing here?

I know the official speed of stock VGA is 25.175 MHz. Which is faster than the 18 MHz I'm calculating but I'm only thinking monochrome.

Finally, at the end of the day, I'm just looking for what speed of RAM I need to get for monochrome (but later, 8bit VGA) display.

Thanks for any pointers.

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PostPosted: Wed Jun 26, 2019 7:02 pm 
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I think the part you're confused on is that a nanosecond is 1/1000,000,000th of a second - a microsecond is 1/1000,000th of a second.


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PostPosted: Wed Jun 26, 2019 7:32 pm 
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Here's a a simpler way to look at this...

The VGA pixel clock is 25.175 MHz. So you need SRAM fast enough to supply 1 pixel every 1000/25.175 = 39.72ns.

Dave


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PostPosted: Wed Jun 26, 2019 7:59 pm 
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Ah! Thanks guys. I knew I was wrong about something. lol

Also, I knew 55ns SRAM wasn't going to cut it. But sounds like the 12-15ns SRAM should be just fine.

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PostPosted: Wed Jun 26, 2019 9:14 pm 
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You'll usually have RAM wider than one bit, which feeds a shift register. So you don't need a 25MHz access, perhaps more like 1/8 or 1/16 of that. Unless your pixels need more than one bit - but it's still the case that you can build a memory 32 bits wide.


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PostPosted: Thu Jun 27, 2019 9:18 am 
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BigEd wrote:
You'll usually have RAM wider than one bit, which feeds a shift register. So you don't need a 25MHz access, perhaps more like 1/8 or 1/16 of that. Unless your pixels need more than one bit - but it's still the case that you can build a memory 32 bits wide.


This ^^^ you'll be doing byte reads, so the ram address will be incrementing every ~320ns which means just about any RAM will do

If you do 8bpp color you will of course need something with less than 40ns access time.
Video access happen with a constantly incrementing address and if you give exclusive access to the video hardware for the duration of a visible frame you will be able to keep the RAM selected and keep /OE asserted for the full frame which means you only need to worry about tAA (aka Address to Data Valid)


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PostPosted: Thu Jun 27, 2019 12:25 pm 
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My first VGA circuit is going to use a low-end FPGA and pull data from RAM during the half-cycle when the CPU isn't using it. Which is why I was thinking I would need fast RAM. But since I'm going monochrome at first (yes...I actually like the way it looks), I figured I wouldn't need as much speed. However, 8bpp is on the radar too.

The good news is that there are really fast SRAM's out there in the 8-12ns range with good sizes if you go SMD. So I'm going to get me one of those TSOP to DIP converters for prototyping.

Wish me luck!

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PostPosted: Fri Jun 28, 2019 2:35 am 
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I find it useful to remember that the BBC Micro did 640x256@50Hz (PAL) with a 16MHz dot clock. This required pulling out 8 bits every 8 pixels, so at 2MHz - the same speed as the CPU. The Phi1 clock phase, unused by the CPU, was used for this, so the video output didn't slow the CPU down at all (unlike *some* early micros we could name).

The BBC Micro used DRAM with the usual multiplexed address bus for that type of memory. This meant it had to provide two addresses per DRAM access - a row address, then a column address. With two accesses per 2MHz clock cycle (one for video, then one for CPU), that meant 4MHz address cycles on the DRAM. In addition to that, part of the address was "scrambled" so that the Teletext mode would still guarantee accesses to all DRAM rows for refresh.

For basic VGA, the standard 25.175MHz dot clock divides to an actual 3.1469 MHz access rate at 1bpp. If you run your 6502 at twice that speed (well within WDC's spec at 3V), and use every other Phi1 cycle to feed your shift register, you can still get away with almost 80ns access time; 55ns gives you some comfort margin.


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